FPGA数字信号处理实现原理及方法代码
所属分类：其他
开发工具：VHDL
文件大小：4705KB
下载次数：2
上传日期：2020-08-01 09:23:20
上 传 者：
libarenzzy
说明： 本光盘是《数字信号处理FPGA实现》一书的配书光盘，内容包括了书中第二章给出的所有示例以及该书的12个实验完整的工程文件。
本光盘根目录下有3个文件夹，分别为dsp48_application,dsp48e_application和DSP_Example。
(This CD-ROM is the CD-ROM of the book "FPGA implementation of digital signal processing". It includes all the examples given in Chapter 2 and the complete engineering documents of 12 experiments in the book.
There are three folders in the root directory of this CD-ROM, which are dsp48_ application,dsp48e_ Application and DSP_ Example.)
文件列表:
FPGA数字信号处理实现原理及方法 (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\DSP_Example (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\DSP_Example\doFFTplot.m (3422, 2009-07-30)
FPGA数字信号处理实现原理及方法\DSP_Example\slblocks.m (544, 2008-01-18)
FPGA数字信号处理实现原理及方法\DSP_Example\test1 (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\DSP_Example\test1\fir1.mdl (71075, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test10 (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\DSP_Example\test10\lms1.mdl (111952, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test10\lms_audio (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\DSP_Example\test10\lms_audio\Yabu_sample_48_mono.wav (1495084, 2008-01-18)
FPGA数字信号处理实现原理及方法\DSP_Example\test10\lms_audio\adaptive_lms1.mdl (30299, 2008-10-24)
FPGA数字信号处理实现原理及方法\DSP_Example\test10\lms_audio\adaptive_lms2.mdl (124409, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test10\lms_transpose.mdl (110513, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test11 (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\audio.mdl (299658, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\costas_loop.mdl (91996, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\early_late.mdl (95222, 2008-09-12)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\generate_audio.mdl (100788, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\loop_filters.mdl (48227, 2008-07-19)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\phase_and_filter.mdl (63346, 2008-07-19)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\phase_detector.mdl (49904, 2008-07-19)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\pll_01 (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\pll_01\phase_detector.mdl (49904, 2008-07-19)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\pll_02 (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\pll_02\loop_filters.mdl (48227, 2008-07-19)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\pll_type2.mdl (77830, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\pll_type2_noise.mdl (77241, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\pll_types_1_and_2.mdl (110721, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\rectangular.mdl (47715, 2008-09-12)
FPGA数字信号处理实现原理及方法\DSP_Example\test11\squaring.mdl (105756, 2008-09-11)
FPGA数字信号处理实现原理及方法\DSP_Example\test2 (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\DSP_Example\test2\asymmetric_8weight.mdl (93085, 2008-11-03)
FPGA数字信号处理实现原理及方法\DSP_Example\test2\even_symmetric_8.mdl (76110, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test2\mux_2channels.mdl (122118, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test2\mux_2channels_pipelined.mdl (128718, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test2\mux_3channels.mdl (142477, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test2\odd_symmetric_9.mdl (82898, 2008-12-17)
FPGA数字信号处理实现原理及方法\DSP_Example\test3 (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\DSP_Example\test3\cordic_cells.mdl (94488, 2008-07-24)
FPGA数字信号处理实现原理及方法\DSP_Example\test3\cordic_cells2.mdl (94488, 2008-07-24)
... ...
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Revision Note
July 12, 2005. Updated Fully Pipelined 35x35 Multiplier codes. The codes are
mult35x35_parallel_pipe.v
mult35x35_parallel_pipe.vhd
August 05, 2005. Updated HDL files for the counter. Set CEC, CECTRL, CECINSUB to 1.
Corrected OPMODE and ADD_SUB definition according to the counter section description in Chapter 2
August 11, 2005. Updated HDL files for accum48, mult35x18_sequential_pipe, and mult35x35_sequential_pipe.
Corrected LEGACY attribute to mult18x18 when MREG is 0
November 27, 2005. Added div_sub_cascade.* files.
January 30, 2006. Remeoved SIM_X_INPUT attribute from the VHDL and Verilog files.
March 10, 2006. Registered OPMODE and SUBTRACT inputs of the DSP48 in the cntr_load.v and cntr_load.vhd files.
May26, 2006. Changed the attribute passing statements in the Verilog codes.
Fixed functional error in fast_sqrt_mult_cascade files.
January 27, 2007 Changed the Barrelshifter code to include 17 bit shifting. This was done by using the SUBTRACT input.
******************************************************************************
basic math function zip (ug073_c02.zip) file contains
Loadable counter design
cntr_load.v
cntr_load.vhd
cntr_load.ucf
Division using multiplier (DSP48 connected in cascaded mode)
div_mult_cascade.v
div_mult_cascade.vhd
div_mult_cascade.ucf
Division using subtrater (DSP48 connected in cascaded mode)
div_sub_cascade.v
div_sub_cascade.vhd
div_sub_cascade.ucf
Square root using multiplier (DSP48 connected in cascaded mode)
sqrt_mult_cascade.v
sqrt_mult_cascade.vhd
sqrt_mult_cascade.ucf
The verilog and vhdl synthesized and places and routed using Foundation 6.2.03i, Application
version G-31. XST ws used for synthesis. All other synthesis and PAR settings were set to
default.
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