ml555_block_plus_example_es
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文件列表:
LogiCORE_Endpoint_Block_Plus_v1.3_EA\ML555_bitstreams (0, 2007-08-24)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\ML555_bitstreams\ml555_x4_x8_file.cfi (439, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\ML555_bitstreams\ml555_x4_x8_file.mcs (11797581, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\ML555_bitstreams\ml555_x4_x8_file.prm (1243, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\ML555_bitstreams\ml555_x4_x8_file.sig (293, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\ML555_bitstreams\pcie_endpoint_plus_4lane_pio.bit (1756619, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\ML555_bitstreams\pcie_endpoint_plus_8lane_pio.bit (1756619, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio (0, 2007-08-24)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3 (0, 2007-08-24)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\doc (0, 2007-08-24)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\doc\pcie_blk_plus_ds551.pdf (498046, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\doc\pcie_blk_plus_gsg343.pdf (312255, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\doc\pcie_blk_plus_ug341.pdf (2281702, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design (0, 2007-08-24)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\EP_MEM.v (65122, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\pci_exp_4_lane_64b_ep.v (7999, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\pci_exp_64b_app.v (11273, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\PIO.v (6355, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\PIO_64.v (114, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\PIO_64_RX_ENGINE.v (19700, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\PIO_64_TX_ENGINE.v (8221, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\PIO_EP.v (8947, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\PIO_EP_MEM_ACCESS.v (11515, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\PIO_TO_CTRL.v (2492, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\xilinx_pci_exp_4_lane_64b_ep.vhd (22330, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\xilinx_pci_exp_4_lane_ep.v (18037, 2007-03-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\xilinx_pci_exp_4_lane_ep_product.v (436, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\xilinx_pci_exp_blk_plus_4_lane_ep-XC5VLX50T-FF1136-1_ES_ML555.ucf (11326, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\example_design\xilinx_pci_exp_blk_plus_4_lane_ep_xc5vlx50t-ff1136-1.ucf (4760, 2007-05-15)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement (0, 2007-08-24)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement\implement.bat (879, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement\implement.sh (1054, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement\results (0, 2007-08-24)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement\results\endpoint_blk_plus_v1_3_top.bld (2884, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement\results\endpoint_blk_plus_v1_3_top.ngc (234771, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement\results\endpoint_blk_plus_v1_3_top.ngd (2796750, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement\results\endpoint_blk_plus_v1_3_top_summary.xml (408, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement\results\endpoint_blk_plus_v1_3_top_usage.xml (474381, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement\results\mapped.map (5027, 2007-05-16)
LogiCORE_Endpoint_Block_Plus_v1.3_EA\pcie_endpoint_plus_4lane_pio\endpoint_blk_plus_v1_3\implement\results\mapped.mrp (118264, 2007-05-16)
... ...
Date: May 16, 2007
Directory Descriptions:
ML555_bitstreams - contains a x4 and x8 bitstream along with PROM
files for the ML555 card with ES silicon.
pcie_endpoint_plus_4lane_pio - Contains the x4 LogiCORE Endpoint Block Plus
v1.3 for PCI Express with the ES silicon patch.
The PIO example design is implemented and found in the
implement\results directory.
pcie_endpoint_plus_8lane_pio - Contains the x8 LogiCORE Endpoint Block Plus
v1.3 for PCI Express with the ES silicon patch.
The PIO example design is implemented and found in the
implement\results directory.
Board LEDs when used with either of the above designs:
LED D1 - On if link is up
LED D2 - On if link is operating in x4 mode
LED D3 - On if link is operating in x8 mode
More Information:
To obtain the latest version of the Block Plus core and/or VHDL example files, please
download and install the latest ISE software and IP Update found at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
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