source
所属分类 :VHDL/FPGA/Verilog
开发工具 :Verilog
文件大小 :6826KB
下载次数 :9
上传日期 :2020-08-09 18:45:16
上 传 者 :
河西小王
说明: altera fpga 实现fft,用fft IP核,有matlab仿真代码 (Altera FPGA implementation of FFT, FFT IP core, matlab simulation code)
文件列表 :
source (0, 2020-08-06) source\fftfilter.v (5232, 2020-08-07) source\fftfilter.v.bak (5123, 2020-08-05) source\iffout.v.bak (3917, 2020-08-05) source\ifftout.v (3918, 2020-08-06) source\IP (0, 2020-08-05) source\IP\FFT (0, 2020-08-07) source\IP\FFT\.qsys_edit (0, 2020-08-07) source\IP\FFT\.qsys_edit\fft256.xml (82562, 2020-08-07) source\IP\FFT\.qsys_edit\fft256_schematic.nlv (684, 2020-08-07) source\IP\FFT\.qsys_edit\filters.xml (66, 2020-08-07) source\IP\FFT\.qsys_edit\preferences.xml (386, 2020-08-07) source\IP\FFT\fft256 (0, 2020-08-07) source\IP\FFT\fft256.qsys (3914, 2020-08-07) source\IP\FFT\fft256.sopcinfo (16438, 2020-08-07) source\IP\FFT\fft256\fft256.bsf (7798, 2020-08-07) source\IP\FFT\fft256\fft256.cmp (1599, 2020-08-07) source\IP\FFT\fft256\fft256.csv (23435, 2020-08-07) source\IP\FFT\fft256\fft256.html (8784, 2020-08-07) source\IP\FFT\fft256\fft256.ppf (1372, 2020-08-07) source\IP\FFT\fft256\fft256.spd (31766, 2020-08-07) source\IP\FFT\fft256\fft256.xml (46393, 2020-08-07) source\IP\FFT\fft256\fft256_bb.v (654, 2020-08-07) source\IP\FFT\fft256\fft256_generation.rpt (4952, 2020-08-07) source\IP\FFT\fft256\fft256_generation_previous.rpt (4952, 2020-08-07) source\IP\FFT\fft256\fft256_inst.v (1233, 2020-08-07) source\IP\FFT\fft256\fft256_inst.vhd (2838, 2020-08-07) source\IP\FFT\fft256\simulation (0, 2020-08-07) source\IP\FFT\fft256\simulation\aldec (0, 2020-08-07) source\IP\FFT\fft256\simulation\aldec\rivierapro_setup.tcl (33407, 2020-08-07) source\IP\FFT\fft256\simulation\cadence (0, 2020-08-07) source\IP\FFT\fft256\simulation\cadence\cds.lib (1729, 2020-08-07) source\IP\FFT\fft256\simulation\cadence\cds_libs (0, 2020-08-07) source\IP\FFT\fft256\simulation\cadence\cds_libs\fft_ii_0.cds.lib (1729, 2020-08-07) source\IP\FFT\fft256\simulation\cadence\hdl.var (18, 2020-08-07) source\IP\FFT\fft256\simulation\cadence\ncsim_setup.sh (14602, 2020-08-07) source\IP\FFT\fft256\simulation\fft256.sip (33408, 2020-08-07) source\IP\FFT\fft256\simulation\fft256.v (2092, 2020-08-07) source\IP\FFT\fft256\simulation\mentor (0, 2020-08-07) source\IP\FFT\fft256\simulation\mentor\msim_setup.tcl (33575, 2020-08-07) ... ...
This is the bit accurate system C model of the FFT Variable streaming
To make the executable
1. make -f Makefile.osci
To run the executable
./SVSfft_model [ ]
where dw = data width
tw = twiddle width
nps = max FFT block size
output order = 0 - bit reverse order, 1 - natural order
input order = 0 - bit reverse order, 1 - natural order
representation = 0 - fixed point, 1 - floating pt
real input file = path to file containing the real input data, defaults to in_real
imag input file = path to file containing the imag input data, defaults to in_imag
blksize file = path to file containing nps for each frame, defaults to all frames of size nps
inverse file = path to file containing fft(0)/ifft(1) for each frame, defaults to fft for all frames
real output file = path to file where the real output data will be written, defaults to out_real
imag output file = path to file where the imag output data will be written, defaults to out_imag
NOTE if the input file contains real and imaginary data alternatively, then set real input file = imag input file. Similarly for the output
files, i.e. if real output file = imag output file, then real and imaginary data will be written alternatively to the same file.
input files are always assumed to be in natural order.
(therefore if input file is in bit-reversed order, set input order to bit-reverse)
eg ./SVSfftmodel 8 8 *** 1 1 0 real_input.txt imag_input.txt blksize_report.txt
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