SPI
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：2227KB
下载次数：3
上传日期：2020-08-16 18:13:47
上 传 者：
JustYouNeed
说明： SPI主机代码,可配置数据宽度，时钟速率。
(SPI Master,Configurable data width, clock rate.)
文件列表:
SPI (0, 2020-05-06)
SPI\Project (0, 2020-08-12)
SPI\Project\fuse.log (1732, 2020-08-10)
SPI\Project\fuse.xmsgs (585, 2020-08-10)
SPI\Project\fuseRelaunch.cmd (244, 2020-08-10)
SPI\Project\ipcore_dir (0, 2020-08-10)
SPI\Project\ipcore_dir\bayer.asy (3320, 2020-08-09)
SPI\Project\ipcore_dir\bayer.gise (1352, 2020-08-09)
SPI\Project\ipcore_dir\bayer.ngc (2046760, 2020-08-09)
SPI\Project\ipcore_dir\bayer.sym (8630, 2020-08-09)
SPI\Project\ipcore_dir\bayer.v (3578640, 2020-08-09)
SPI\Project\ipcore_dir\bayer.veo (5632, 2020-08-09)
SPI\Project\ipcore_dir\bayer.xco (1585, 2020-08-09)
SPI\Project\ipcore_dir\bayer.xise (4880, 2020-08-09)
SPI\Project\ipcore_dir\bayer_flist.txt (175, 2020-08-09)
SPI\Project\ipcore_dir\bayer_xmdf.tcl (2630, 2020-08-09)
SPI\Project\ipcore_dir\coregen.cgp (237, 2020-08-09)
SPI\Project\ipcore_dir\coregen.log (240, 2020-08-10)
SPI\Project\ipcore_dir\create_bayer.tcl (1289, 2020-08-09)
SPI\Project\ipcore_dir\create_dds.tcl (1255, 2020-08-10)
SPI\Project\ipcore_dir\create_fsdf.tcl (1288, 2020-08-09)
SPI\Project\ipcore_dir\create_gh.tcl (1254, 2020-08-10)
SPI\Project\ipcore_dir\edit_bayer.tcl (1120, 2020-08-09)
SPI\Project\ipcore_dir\tmp (0, 2020-08-10)
SPI\Project\ipcore_dir\tmp\bayer.lso (6, 2020-08-09)
SPI\Project\ipcore_dir\tmp\_cg (0, 2020-08-10)
SPI\Project\ipcore_dir\tmp\_cg\_dbg (0, 2020-08-10)
SPI\Project\ipcore_dir\tmp\_cg\_dbg\xil_693.in (1873, 2020-08-10)
SPI\Project\ipcore_dir\tmp\_cg\_dbg\xil_693.out (150, 2020-08-10)
SPI\Project\ipcore_dir\tmp\_xmsgs (0, 2020-08-09)
SPI\Project\ipcore_dir\tmp\_xmsgs\netgen.xmsgs (665, 2020-08-09)
SPI\Project\ipcore_dir\tmp\_xmsgs\pn_parser.xmsgs (769, 2020-08-09)
SPI\Project\ipcore_dir\tmp\_xmsgs\xst.xmsgs (22438, 2020-08-09)
SPI\Project\ipcore_dir\xlnx_auto_0_xdb (0, 2020-08-09)
SPI\Project\ipcore_dir\_xmsgs (0, 2020-08-10)
SPI\Project\ipcore_dir\_xmsgs\cg.xmsgs (678, 2020-08-10)
SPI\Project\ipcore_dir\_xmsgs\pn_parser.xmsgs (761, 2020-08-09)
SPI\Project\iseconfig (0, 2020-07-16)
SPI\Project\iseconfig\filter.filter (650, 2020-07-16)
... ...
The following files were generated for 'bayer' in directory
F:\FPGA\Module\SPI\Project\ipcore_dir\
Generate XCO file:
CORE Generator input file containing the parameters used to generate a core.
* bayer.xco
Generate Implementation Netlist:
Binary Xilinx implementation netlist files containing the information
required to implement the module in a Xilinx (R) FPGA.
* bayer.ngc
Obfuscate Netlist Generator:
Please see the core data sheet.
* bayer.ngc
Generate Instantiation Templates:
Template files containing code that can be used as a model for instantiating
a CORE Generator module in an HDL design.
* bayer.veo
TCL Flow Generator:
Structural simulation model generator
* bayer.v
Deliver IP Symbol:
Graphical symbol information file. Used by the ISE tools and some third party
tools to create a symbol representing the core.
* bayer.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* bayer.sym
Coregen XMDF Generator:
XMDF generator
* bayer_xmdf.tcl
Synthesis ISE Generator:
Please see the core data sheet.
* bayer.gise
* bayer.xise
Generate ISE project file:
ISE Project Navigator support files. These are generated files and should not
be edited directly.
* bayer.gise
* bayer.xise
Deliver Readme:
Readme file for the IP.
* bayer_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* bayer_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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