sdram_controller_sim
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：2091KB
下载次数：2
上传日期：2020-08-26 20:59:39
上 传 者：
cz50534
说明： 包含sdram controller的源文件以及仿真文件
(Contains the source file and simulation file of SDRAM controller)
文件列表:
sdram_controller_sim\doc\micron_sdram.pdf (1843200, 2001-09-26)
sdram_controller_sim\part1\part1_32\model\mt48lc2m32b2.v (50092, 2004-09-03)
sdram_controller_sim\part1\part1_32\rtl\Command.v (17532, 2005-06-18)
sdram_controller_sim\part1\part1_32\rtl\control_interface.v (8494, 2004-11-28)
sdram_controller_sim\part1\part1_32\rtl\Params.v (935, 2005-06-14)
sdram_controller_sim\part1\part1_32\rtl\sdr_data_path.v (2760, 2004-08-02)
sdram_controller_sim\part1\part1_32\rtl\sdr_sdram.v (7233, 2005-06-14)
sdram_controller_sim\part1\part1_32\sim\Command.v (17532, 2005-06-18)
sdram_controller_sim\part1\part1_32\sim\control_interface.v (8494, 2004-11-28)
sdram_controller_sim\part1\part1_32\sim\mt48lc2m32b2.v (50092, 2004-09-03)
sdram_controller_sim\part1\part1_32\sim\Params.v (935, 2005-06-14)
sdram_controller_sim\part1\part1_32\sim\sd32try.cr.mti (2161, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\sd32try.mpf (23068, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\sdram_test_tb.v (7746, 2005-11-22)
sdram_controller_sim\part1\part1_32\sim\sdr_data_path.v (2760, 2004-08-02)
sdram_controller_sim\part1\part1_32\sim\sdr_sdram.v (7233, 2005-06-14)
sdram_controller_sim\part1\part1_32\sim\sdtry.cr.mti (1979, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\vsim.wlf (32768, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\wave.do (2648, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\command\verilog.asm (37891, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\command\_primary.dat (4825, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\command\_primary.vhd (1319, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\control_interface\verilog.asm (22288, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\control_interface\_primary.dat (2787, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\control_interface\_primary.vhd (1105, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\mt48lc2m32b2\verilog.asm (262084, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\mt48lc2m32b2\_primary.dat (27748, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\mt48lc2m32b2\_primary.vhd (1291, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\sdram_test_tb\verilog.asm (59065, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\sdram_test_tb\_primary.dat (6183, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\sdram_test_tb\_primary.vhd (1441, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\sdr_data_path\verilog.asm (5465, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\sdr_data_path\_primary.dat (798, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\sdr_data_path\_primary.vhd (502, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\sdr_sdram\verilog.asm (21541, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\sdr_sdram\_primary.dat (2875, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\sdr_sdram\_primary.vhd (877, 2006-10-15)
sdram_controller_sim\part1\part1_32\sim\work\_info (1818, 2006-10-15)
sdram_controller_sim\part1\part1_32\test_bench\sdram_test_tb.v (7746, 2005-11-22)
sdram_controller_sim\part1\part1_32\wave\32wave.bmp (2359350, 2006-10-15)
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