随机数产生源程序
所属分类:VHDL/FPGA/Verilog
开发工具:Verilog
文件大小:91KB
下载次数:2
上传日期:2020-08-26 21:01:53
上 传 者:
cz50534
说明: 伪随机数产生代码以及说明文件,用于产生伪随机数
(Pseudo random number generation code and description file, used to generate pseudo-random number)
文件列表:
verilog\CVS\Entries (42, 2008-09-11)
verilog\CVS\Entries.Extra (16, 2008-09-11)
verilog\CVS\Entries.Extra.Old (0, 2008-09-11)
verilog\CVS\Entries.Old (0, 2008-09-11)
verilog\CVS\Repository (25, 2008-09-11)
verilog\CVS\Root (57, 2008-09-11)
verilog\CVS\Template (0, 2008-09-11)
verilog\rng.v (9668, 2005-09-16)
verilog\CVS (0, 2008-09-11)
verilog (0, 2008-09-11)
verilog\Tkacik.pdf (170063, 2008-09-11)
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