digital_recognition
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：46506KB
下载次数：12
上传日期：2020-09-09 12:50:13
上 传 者：
蓝灵
说明： 基于FPGA平台，实现视频图像中的数字识别
(Based on FPGA platform, digital recognition in video image is realized)
文件列表:
digital_recognition (0, 2020-09-05)
digital_recognition\DE1_SoC_TV (0, 2020-09-05)
digital_recognition\DE1_SoC_TV\.qsys_edit (0, 2020-09-05)
digital_recognition\DE1_SoC_TV\.qsys_edit\filters.xml (66, 2018-06-21)
digital_recognition\DE1_SoC_TV\.qsys_edit\preferences.xml (347, 2018-06-21)
digital_recognition\DE1_SoC_TV\aldec (0, 2020-09-05)
digital_recognition\DE1_SoC_TV\aldec\rivierapro_setup.tcl (10793, 2018-06-21)
digital_recognition\DE1_SoC_TV\c5_pin_model_dump.txt (4757, 2018-06-21)
digital_recognition\DE1_SoC_TV\cadence (0, 2020-09-05)
digital_recognition\DE1_SoC_TV\cadence\cds.lib (1297, 2018-06-21)
digital_recognition\DE1_SoC_TV\cadence\hdl.var (18, 2018-06-21)
digital_recognition\DE1_SoC_TV\cadence\ncsim_setup.sh (8382, 2018-06-21)
digital_recognition\DE1_SoC_TV\chunklib (0, 2020-09-05)
digital_recognition\DE1_SoC_TV\chunklib\address_gen.v (555, 2018-06-21)
digital_recognition\DE1_SoC_TV\chunklib\address_gen.v.bak (495, 2018-06-21)
digital_recognition\DE1_SoC_TV\chunklib\clk_div.v (353, 2018-06-21)
digital_recognition\DE1_SoC_TV\chunklib\clk_div.v.bak (352, 2018-06-21)
digital_recognition\DE1_SoC_TV\chunklib\div_even.v (470, 2018-06-21)
digital_recognition\DE1_SoC_TV\chunklib\div_odd.v (622, 2018-06-21)
digital_recognition\DE1_SoC_TV\chunklib\freq_meters.v (1563, 2018-06-21)
digital_recognition\DE1_SoC_TV\cio_dump_disallowed_lists.echo (57888, 2018-06-21)
digital_recognition\DE1_SoC_TV\db (0, 2020-09-05)
digital_recognition\DE1_SoC_TV\db\.cmp.kpt (4211, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\.ipregen.qmsg (6052, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_0ic.tdf (1542, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_1ic.tdf (1543, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_9jc.tdf (1546, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_ajc.tdf (1550, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_bjc.tdf (1550, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_cjc.tdf (1550, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_djc.tdf (1550, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_ejc.tdf (1550, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_fjc.tdf (1550, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_gjc.tdf (1550, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_hjc.tdf (1550, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_qhc.tdf (1542, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_shc.tdf (1542, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_thc.tdf (1542, 2018-06-21)
digital_recognition\DE1_SoC_TV\db\add_sub_uhc.tdf (1542, 2018-06-21)
... ...
# digital_rcognition
#### Introduction
This is the code which implements digital recognition based on FPGA.
#### Tool
1、Quartus 17.1
2、Python, Modelsim(use while simulation)
3、Matlab 2017a(use to change jpg to mif)
#### Platform
DE1_SOC(Cyclone V FPGA + ARM Cortex-A9)
#### Folder
1.DE1_SoC_TV: all the source code of this project
2.Material: image resource of the project
3.pdf: some reference document about the project
4.result_image: the result of simulation and actual test
5.simulation: the simulation code of each module of this project(include matlab and modelsim simulation)
#### Copyright
Kewei Xia, TangBo Liu
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