说明：  LDPC 译码算法主要研究了基于概率测度的BP 译码算法、基于LLR 的BP 译码算法、归一化最小和译码算法等算法。最终的实现选择了适合 FPGA 硬件实现的归一化最小和译码算法。在实现结构方面，对 TPMP 和 TDMP 两种实现结构进行了仿真对比，最终选择了收敛速度快、迭代次数少的 TDMP 实现结构，即水平分层迭代结构。最终实现的译码器可以信噪比为 2.5d B 时，BER 可以达到10-6。另外，为了实现高速译码器的目标，译码器的实现过程中采用了乒乓操作、流水线结构、四个码字同时译码等结构来提高译码器的吞吐率。
(LDPC decoding algorithm mainly studies BP decoding algorithm based on probability measure, BP decoding algorithm based on LLR, normalized minimum sum decoding algorithm and so on. Finally, the normalized minimum sum decoding algorithm suitable for FPGA hardware implementation is selected. In the aspect of implementation structure, tpmp and tdmp are simulated and compared. Finally, tdmp implementation structure with fast convergence speed and less iteration times is selected, that is horizontal layered iterative structure. The final decoder can achieve BER of 10-6 when SNR is 2.5dB. In addition, in order to achieve the goal of high-speed decoder, ping-pong operation, pipeline structure and simultaneous decoding of four codewords are used to improve the throughput of the decoder.)