说明：  本文针对部分并行结构的准循环LDPC码译码器，提出了一种将译码准码字存储在信道信息和外信息存储块中的高效存储方法，该方法可减少译码器对存储资源的需求量，并降低了译码电路的布线复杂度；另外，本文通过分析 LDPC 码译码的循环迭代过程，一种变量节点处理单元和校验节点处理单元完全并行交替处理两数据帧的译码器结构，在该结构的基础上提出了一种动态的地址访问管理方法，设计得到的译码器能够在 FPGA 资源需求量不变的基础上将译码吞吐量提高约一倍；针对传统迭代次数固定的译码器设计方法，本文还给出了一种迭代次数可变的 LDPC 码译码器设计方法，该方法能够减少译码所需的总时钟周期数，适合实时性要求较高的译码器实现.
(In this paper, an efficient storage method for quasi cyclic LDPC decoder with partially parallel structure is proposed, which stores the decoded quasi code words in channel information and external information storage blocks. This method can reduce the storage resource requirement of the decoder and reduce the wiring complexity of decoding circuit. In addition, this paper analyzes the LDPC code by analyzing the performance of the decoder In this paper, we propose a dynamic address access management method based on the structure. The decoder can be implemented in parallel with the variable node processing unit and the check node processing unit In this paper, a LDPC decoder design method with variable iterations is proposed, which can reduce the total clock cycles required for decoding, and is suitable for decoder implementation with high real-time requirements .)