verifying-foss-hdl-synthesizers
所属分类：大数据
开发工具：Makefile
文件大小：22KB
下载次数：0
上传日期：2020-09-26 16:58:21
上 传 者：
sh-1993
说明： 验证福斯hdl合成器，这是一个根据供应商EDA工具检查福斯合成器的项目
(verifying-foss-hdl-synthesizers,a project to check the FOSS synthesizers against vendors EDA tools)
文件列表:
Dockerfile (426, 2020-09-27)
FPGADesignElements (0, 2020-09-27)
FPGADesignElements\Makefile (5145, 2020-09-27)
LICENSE (759, 2020-09-27)
Makefile (358, 2020-09-27)
helpers (0, 2020-09-27)
helpers\docker_run.sh (162, 2020-09-27)
helpers\getcomp.py (1087, 2020-09-27)
helpers\ghdl.sh (499, 2020-09-27)
issues.md (3149, 2020-09-27)
xilinx (0, 2020-09-27)
xilinx\Makefile (2092, 2020-09-27)
xilinx\Makeghdl (13705, 2020-09-27)
xilinx\Makeyosys (9433, 2020-09-27)
xilinx\support (0, 2020-09-27)
xilinx\support\EvenSymTranspConvFIR.diff (326, 2020-09-27)
xilinx\support\OddSymTranspConvFIR.diff (325, 2020-09-27)
xilinx\support\blackboxes.v (508, 2020-09-27)
xilinx\support\blackboxes.vhd (704, 2020-09-27)
xilinx\support\fileread_endfile.diff (688, 2020-09-27)
xilinx\support\nonlrm_bufferout.diff (542, 2020-09-27)
xilinx\support\nonlrm_outbuffer.diff (514, 2020-09-27)
xilinx\support\ram_protected_sharedvar.diff (748, 2020-09-27)
xilinx\support\rams_20c.diff (746, 2020-09-27)
xilinx\support\rams_init_file.diff (465, 2020-09-27)
xilinx\support\roms_1.diff (1666, 2020-09-27)
# Verifying FOSS HDL-synthesizers
The aim of this project is to provide feedback about things supported by the vendor EDA tools, which presents [issues](issues.md) for [Yosys](https://github.com/YosysHQ/yosys), [GHDL](https://github.com/ghdl/ghdl) or [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin). This is performed, running the tools against several examples from different sources:
* [xilinx](xilinx): Verilog and VHDL examples for ISE and Vivado, provided by Xilinx.
* [FPGADesignElements](FPGADesignElements): a [online book](https://github.com/laforest/FPGADesignElements) containing a library of FPGA Verilog design modules.
Firstly, the examples are checked with commercial tools such as ISE, Vivado and Quartus, to check if they are synthesizable.
Secondly, they are analyzed with tools like iVerilog and GHDL to detect non-standard constructions.
Then, the tools under test are employed. If an issue is detected, it is reported and the file is ignored until fixed.
To simplify tools and options handling, `fpga-hdl2bit` from the [PyFPGA](https://gitlab.com/rodrigomelo9/pyfpga) project is used (when supported).
A Dockerfile, based on `ghdl/synth:beta` from the [ghdl/docker](https://github.com/ghdl/docker) project (which supports the three tools under test), is provided.
It is employed for the CI of the repository and can be used to run in any GNU/Linux with [Docker installed](https://docs.docker.com/install) on:
* `make build` creates the needed Docker image.
* `bash helpers/docker_run.sh make clean-all` to clean the generated files of a previous run.
* `make prepare` downloads the examples (they are not part of the repository).
* `bash helpers/docker_run.sh make verify-yosys` to verify `yosys`.
* `bash helpers/docker_run.sh make verify-ghdl` to verify `ghdl --synth`.
* `bash helpers/docker_run.sh make verify-ghdl-yosys` to verify `ghdl-yosys-plugin`.
## License
This project is distributed under [ISC](LICENSE) license.
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