HomebrewAurora-master
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：202KB
下载次数：0
上传日期：2020-09-29 23:23:41
上 传 者：
fengxu7203
说明： crc eth网的，里面有代码，还有文字，图片等信息
(Crc eth network, which has code, text, pictures and other information)
文件列表:
LICENSE (1061, 2018-08-21)
Manifest.py (96, 2018-08-21)
RX (0, 2018-08-21)
RX\Manifest.py (196, 2018-08-21)
RX\aurora_rx_lane.vhd (16759, 2018-08-21)
RX\descrambler.v (2412, 2018-08-21)
RX\gearbox32to66.vhd (2153, 2018-08-21)
RX\xapp1017 (0, 2018-08-21)
RX\xapp1017\delay_controller_wrap.vhd (18736, 2018-08-21)
RX\xapp1017\serdes_1_to_468_idelay_ddr.vhd (21937, 2018-08-21)
TX (0, 2018-08-21)
TX\Manifest.py (153, 2018-08-21)
TX\aurora_tx_lane128.vhd (4680, 2018-08-21)
TX\gearbox66to32.vhd (5969, 2018-08-21)
TX\scrambler.v (1342, 2018-08-21)
TX\serdes32to8.vhd (2542, 2018-08-21)
TX\serdes8to1.vhd (2534, 2018-08-21)
Testing (0, 2018-08-21)
Testing\Manifest.py (95, 2018-08-21)
Testing\comparator.vhd (4889, 2018-08-21)
Testing\generator.vhd (3268, 2018-08-21)
Testing\loopback128gbps.vhd (7384, 2018-08-21)
doc (0, 2018-08-21)
doc\lane_tst.png (22720, 2018-08-21)
doc\txrx_blocks.png (183099, 2018-08-21)
# HomebrewAurora
A custom made Aurora ***b/66b transmitter and receiver
## Data Flow
The data passes through multiples steps, all based on the original ***b/66b Aurora.
## Testing
To ensure the operation of the components a loopback test is available. It adds a generator and a comparator and allow to check elements such as the proper alignement of the TX / RX interfaces and the transmission errors
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