16x4-6T-SRAM-Memory-Block-master
所属分类：DSP编程
开发工具：LINUX
文件大小：322KB
下载次数：0
上传日期：2020-11-02 08:02:01
上 传 者：
takrony
说明： code for design sram cell
文件列表:
SRAM\Buffer\extracted\layout.cdb (5627, 2018-01-16)
SRAM\Buffer\extracted\master.tag (39, 2018-01-16)
SRAM\Buffer\extracted\pc.db (140, 2018-01-16)
SRAM\Buffer\layout\layout.cdb (3057, 2018-01-16)
SRAM\Buffer\layout\master.tag (39, 2018-01-16)
SRAM\Buffer\layout\pc.db (54, 2018-01-16)
SRAM\Buffer\prop.xx (3156, 2018-01-16)
SRAM\Buffer\schematic\master.tag (36, 2018-01-16)
SRAM\Buffer\schematic\pc.db (253, 2018-01-16)
SRAM\Buffer\schematic\prop.xx (780, 2018-01-16)
SRAM\Buffer\schematic\sch.cdb (5557, 2018-01-16)
SRAM\Buffer\symbol\master.tag (39, 2018-01-16)
SRAM\Buffer\symbol\symbol.cdb (1173, 2018-01-16)
SRAM\cdsinfo.tag (1339, 2018-01-16)
SRAM\Col_Decoder\extracted\layout.cdb (21495, 2018-01-16)
SRAM\Col_Decoder\extracted\master.tag (39, 2018-01-16)
SRAM\Col_Decoder\extracted\pc.db (249, 2018-01-16)
SRAM\Col_Decoder\layout\layout.cdb (13913, 2018-01-16)
SRAM\Col_Decoder\layout\master.tag (39, 2018-01-16)
SRAM\Col_Decoder\layout\pc.db (111, 2018-01-16)
SRAM\Col_Decoder\prop.xx (3560, 2018-01-16)
SRAM\Col_Decoder\schematic\master.tag (36, 2018-01-16)
SRAM\Col_Decoder\schematic\pc.db (221, 2018-01-16)
SRAM\Col_Decoder\schematic\prop.xx (628, 2018-01-16)
SRAM\Col_Decoder\schematic\sch.cdb (11965, 2018-01-16)
SRAM\Col_Decoder\symbol\master.tag (39, 2018-01-16)
SRAM\Col_Decoder\symbol\symbol.cdb (1884, 2018-01-16)
SRAM\Inverter\extracted\layout.cdb (3327, 2018-01-16)
SRAM\Inverter\extracted\master.tag (39, 2018-01-16)
SRAM\Inverter\extracted\pc.db (125, 2018-01-16)
SRAM\Inverter\layout\layout.cdb (1667, 2018-01-16)
SRAM\Inverter\layout\master.tag (39, 2018-01-16)
SRAM\Inverter\layout\pc.db (51, 2018-01-16)
SRAM\Inverter\prop.xx (3064, 2018-01-16)
SRAM\Inverter\schematic\master.tag (36, 2018-01-16)
SRAM\Inverter\schematic\pc.db (214, 2018-01-16)
SRAM\Inverter\schematic\prop.xx (660, 2018-01-16)
SRAM\Inverter\schematic\sch.cdb (3408, 2018-01-16)
SRAM\Inverter\symbol\master.tag (39, 2018-01-16)
... ...
# 16x4 6T SRAM Memory Block
The layout of a *** bit (16x4) 6T SRAM memory block using Cadence Virtuoso is available in this repostiory.
The design was optimized for minimum area and access times, using the TSMC 240nm CMOS process technology.
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