文件列表:

6T_layout.JPG (152865, 2019-02-15)
6T_schematic.JPG (109034, 2019-02-15)
Arch_SRAM.PNG (135773, 2019-02-15)
DFF.JPG (63113, 2019-02-15)
IO_SRAM.PNG (20258, 2019-02-15)
Images (0, 2019-02-15)
Images\6T_layout.JPG (152865, 2019-02-15)
Images\6T_schematic.JPG (109034, 2019-02-15)
Images\DFF.JPG (63113, 2019-02-15)
Images\banksel_lay.JPG (437661, 2019-02-15)
Images\banksel_schem.JPG (116060, 2019-02-15)
Images\buffer_schem.JPG (120407, 2019-02-15)
Images\pre_ckt_cell_lay.JPG (261474, 2019-02-15)
Images\pre_ckt_cell_schem.JPG (80297, 2019-02-15)
Images\readmux_full_schem.JPG (363627, 2019-02-15)
Images\readmuxcell_lay.JPG (251916, 2019-02-15)
Images\readmuxcell_schem.JPG (160537, 2019-02-15)
Images\reg1.JPG (35355, 2019-02-15)
Images\reg2.JPG (91965, 2019-02-15)
Images\rowdecoder_lay.JPG (326650, 2019-02-15)
Images\rowdecoder_schem.JPG (167415, 2019-02-15)
Images\senseamp_full_lay.JPG (234492, 2019-02-15)
Images\senseamp_full_schem.JPG (36829, 2019-02-15)
Images\senseamp_full_schem2.JPG (103779, 2019-02-15)
Images\senseampcell_lay.JPG (135871, 2019-02-15)
Images\senseampcell_schem.JPG (91688, 2019-02-15)
Images\sram_512kb_schem.JPG (109056, 2019-02-15)
Images\sram_512kb_schem2.JPG (294209, 2019-02-15)
Images\sram_512kb_schem3.JPG (432159, 2019-02-15)
Images\sram_512kb_schem_with components.jpg (171854, 2019-02-15)
Images\sram_bank_layout.JPG (600991, 2019-02-15)
Images\sram_bank_schem.JPG (168184, 2019-02-15)
Images\sram_bank_schem2.JPG (223599, 2019-02-15)
Images\sram_cell_test.JPG (93335, 2019-02-15)
Images\sramcelltestckt_schem.JPG (93817, 2019-02-15)
Images\write_mux_full_schem.JPG (368396, 2019-02-15)
Images\writeckt_full_lay.JPG (156608, 2019-02-15)
Images\writeckt_full_schem.JPG (39416, 2019-02-15)
Images\writeckt_lay.JPG (182870, 2019-02-15)
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**_512-Bit-SRAM_** **Steps to Design 512-Bit SRAM** 1) Precharge circuit, 6T SRAM cell, Sense Amplifier and Write Circuit were designed along with dummy transistors and the write data path circuit was designed to test the single cell functionality. 2) A column of the bank with 8 SRAM cells along with the precharge, sense amplifier and write circuit, was tested before making the bank. 3) Write and Read multiplexers were designed using the given specifications. 4) The 128 bit (8 x 16) bank was developed and its working was tested by writing a 16-bit value and reading it out. 5) Bank select and row decoders were designed and it was verified if the output select signals were correct. 6) A 16-bit Register was designed using 16 D flip-flops in order to register the data to be read. 7) The final schematic was rigged and a buffer was added between the Sense Amplifier output and the Register input in order to provide sufficient time for the Register to latch its input. 8) The final schematic was simulated with a vector file as input and the outputs were verified. 9) Layouts for all the basic components were successfully designed and LVS was verified but had issues with the final layout and was unable to complete it. **512-Bit SRAM architecture** **SRAM Architecture**  **Input and output Specification**  **Sense Amplifier**  **Write Data Path**  **Single Bit SRAM design**  The SRAM cell is designed using the 6T model and the sizing is as follows: Pull-up Transistors : Length--> 200nm, Height--> 400nm Pull “down Transistors : Length--> 200nm, Height--> 600nm Access Transistors: Length--> 200nm, Height--> 400nm **One-Bit SRAM **  **Layout Designs:** **1)Sense Amplifier**  **2)Write Circuit**  **3)PreCharge Circuit**  **4)Bank select**  **5)Row Decoder**  **6)SRAM Bank**  **7)Read Mux  **8)Write Mux****  **9)6T SRAM** 

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