DOP2
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：301KB
下载次数：0
上传日期：2020-11-24 18:03:54
上 传 者：
ancirl
说明： a drive using FPGA and microcontroller technology. The process data channel is very time critical. This functionality should be realized in h
文件列表:
ack_no_return.bsf (2089, 2020-04-11)
ack_no_return.vhd (695, 2020-05-06)
ack_no_return.vhd.bak (403, 2020-04-11)
output_files (0, 2020-11-24)
output_files\main.asm.rpt (5097, 2020-11-20)
output_files\main.cdf (359, 2020-11-20)
output_files\main.done (26, 2020-11-20)
output_files\main.eda.rpt (6317, 2020-11-20)
output_files\main.fit.rpt (397282, 2020-11-20)
output_files\main.fit.smsg (703, 2020-11-20)
output_files\main.fit.summary (654, 2020-11-20)
output_files\main.flow.rpt (17323, 2020-11-20)
output_files\main.jdi (5493, 2020-11-20)
output_files\main.map.rpt (443963, 2020-11-20)
output_files\main.map.summary (499, 2020-11-20)
output_files\main.pin (23402, 2020-11-20)
output_files\main.pof (84232, 2020-11-20)
output_files\main.pow.rpt (110290, 2020-11-20)
output_files\main.pow.summary (514, 2020-11-20)
output_files\main.sld (383, 2020-11-20)
output_files\main.sof (262399, 2020-11-20)
output_files\main.sta.rpt (236879, 2020-11-20)
output_files\main.sta.summary (1631, 2020-11-20)
output_files\main.vhd (2489, 2020-11-20)
output_files\stp2.stp (40668, 2020-11-20)
output_files\TEST.vhd (297, 2020-11-20)
output_files\TEST.vhd.bak (13710, 2020-11-20)
simulation (0, 2020-11-24)
simulation\modelsim (0, 2020-11-24)
simulation\modelsim\main.sft (40, 2020-11-20)
simulation\modelsim\main.vho (2368001, 2020-11-20)
simulation\modelsim\main_modelsim.xrf (556749, 2020-11-20)
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