文件列表:

cpu-pipelined (0, 2020-11-28)
cpu-pipelined\Makefile (1865, 2020-11-28)
cpu-pipelined\datapath.v (9004, 2020-11-28)
cpu-pipelined\exmem.v (1186, 2020-11-28)
cpu-pipelined\forward.v (2113, 2020-11-28)
cpu-pipelined\hazard.v (798, 2020-11-28)
cpu-pipelined\idex.v (1774, 2020-11-28)
cpu-pipelined\ifid.v (439, 2020-11-28)
cpu-pipelined\memwb.v (1266, 2020-11-28)
cpu-singlecycle (0, 2020-11-28)
cpu-singlecycle\Makefile (1762, 2020-11-28)
cpu-singlecycle\datapath.v (4703, 2020-11-28)
include (0, 2020-11-28)
include\aluop.vh (219, 2020-11-28)
include\bus.vh (515, 2020-11-28)
include\control.vh (719, 2020-11-28)
include\flags.vh (182, 2020-11-28)
include\forward.vh (264, 2020-11-28)
include\memory.vh (156, 2020-11-28)
include\movop.vh (219, 2020-11-28)
include\opcode.vh (1591, 2020-11-28)
include\registers.vh (149, 2020-11-28)
modules (0, 2020-11-28)
modules\alu.v (1720, 2020-11-28)
modules\branchcontrol.v (2071, 2020-11-28)
modules\controlunit.v (4396, 2020-11-28)
modules\flagsreg.v (372, 2020-11-28)
modules\memdata.v (1094, 2020-11-28)
modules\memprog.v (314, 2020-11-28)
modules\mov.v (689, 2020-11-28)
modules\programcounter.v (409, 2020-11-28)
modules\registerfile.v (981, 2020-11-28)
modules\signextension.v (1132, 2020-11-28)
samples (0, 2020-11-28)
... ...

LEGv8 ===== This repository contains two implementations of a LEGv8 CPU; it also contains some tools written in AWK used to test the CPU: a simple LEGv8 assembler and a verilog testbench generator. It is the final project of the Computer Organization and Architecture course of the Computer Science department of the University of Brasilia. LEGv8 is a simple subset of the ARMv8 AArch*** architecture; it is a ***-bit architecture that uses 32-bit instructions. It has 32 registers, each ***-bits wide, (one of them always zero). To simplify the design, this CPU uses the Harvard memory architecture; this architecture uses two memories: one for the program itself (the instruction memory) and another for the data the program uses (the data memory). It differs from the Von Neumann architecture in which there is a single memory. All files are in public domain. ## FILES * `CPU-pipelined`: A pipelined implementation of a LEGv8 CPU, with hazard detection and forwarding. * `CPU-singlecycle`: A single-cycle implementation of a LEGv8 CPU. * `include`: Headers defining constants such as bus sizes and opcodes. * `modules`: Modules shared by all implementations. * `samples`: Sample programs written in LEGv8 assembly. * `tools`: AWK tools (an assembler and a testbench generator). ## USAGE **Step 1: Assemble the program.** First, to test a CPU, a program should be assembled in order to be load into its memory. The directory `samples/` contains simple programs that can be assembled with the AWK assembler located in `tools/asm`. For example, the following command assembles the program sumtwo.s, which sum the first two values in memory into the register X0. $ cd samples $ ../tools/asm sumtwo.s This command generates two files: sumtwo.text and sumtwo.data. sumtwo.text contains the machine code of the program instructions. sumtwo.data contains the raw data used by the program. To automate the process, the Makefile in the directory `samples/` assembles all programs and generate both files for each of them. $ cd samples $ make **Step 2: Generate the testbench.** To test the CPU, a testbench should be generated to pulse the clock the CPU uses. The directory `cpu-singlecycle/` contains the datapath for a single-cycle CPU. The datapath is the main module of the CPU, that instantiate all other modules. In this directory, run the testbench generator at `tools/tbgen` to generate a testbench for this CPU. The following command do this, but do not run it yet, we'll improve this command with some arguments later. $ cd cpu-singlecycle $ ../tools/tbgen datapath.v > testbench.v This command will fail, since the datapath module needs some data in the files in the directory ../include. To specify this directory, we need to add the following argument: -v incdir=../include This command generates a file `testbench.v` that, when simulated, will create a file called `testbench.vcd` containing the waveforms of the CPU. But this waveform is useless, it only shows waves for the inputs controlled by the testbench, which are the clock and the reset signals. To dump waveforms for more signals, we need to set the dumplevel to 3: thus we will dump the signals of the testbench itself, the module under test (datapath.v) and the modules instanciated by the module under test. The following argument do this -v dumplevel=3 In addition to the waveforms of the signals of the CPU, we can dump the contents of the data memory and the registers of the CPU at the end of the simulation. The contents of the data memory are in the array `memdata.data`, and the contents of the registers are in the array `registerfile.registers`. The following arguments for `tools/tbgen` dump the contents of the data memory into the file `memory.dump` and the contents of the registers into the file `registers.dump`. dump:registerfile.registers:registers.dump \ dump:memdata.data:memory.dump Assembling all arguments, we got the following command. $ cd cpu-singlecycle $ ../tools/tbgen -v incdir=../include \ -v dumplevel=3 \ dump:registerfile.registers:registers.dump \ dump:memdata.data:memory.dump \ datapath.v \ >testbench.v To automate this step, the Makefile in the directory `cpu-singlecycle/` can generate the testbench for the datapath with the following command. $ cd cpu-singlecycle $ make testbench.v **Step 3: Run the simulation.** To run the simulation, we must first run iverilog(1) to compile the sources of the datapath and the modules used by it (located at `../modules`). Then, run vvp(1) to do the simulation and generate the files `testbench.vcd` (which contains the waveforms), `registers.dump` (which contains the contents of the registers) and `memory.dump` (which contains the contents of the registers). The following commands do it, it will generate the file `testbench`, which we can delete after running vvp(1). But don't run these commands yet, as they will fail. $ cd cpu-singlecycle $ iverilog -s testbench -o testbench testbench.v datapth.v ../modules/*.v $ vvp testbench

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