project_44_12345678
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：1053KB
下载次数：1
上传日期：2020-11-29 14:47:34
上 传 者：
hoity11
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文件列表:
project_44_12345678 (0, 2020-11-29)
project_44_12345678\.Xil (0, 2020-11-29)
project_44_12345678\.Xil\Vivado-7600-LAPTOP-RGN4NOAJ (0, 2020-11-29)
project_44_12345678\.Xil\Vivado-7600-LAPTOP-RGN4NOAJ\wave (0, 2020-11-29)
project_44_12345678\hs_err_pid7600.dmp (342954, 2020-11-29)
project_44_12345678\hs_err_pid7600.log (143, 2020-11-29)
project_44_12345678\project_44_12345678.cache (0, 2020-11-29)
project_44_12345678\project_44_12345678.cache\compile_simlib (0, 2020-10-14)
project_44_12345678\project_44_12345678.cache\compile_simlib\activehdl (0, 2020-11-29)
project_44_12345678\project_44_12345678.cache\compile_simlib\ies (0, 2020-11-29)
project_44_12345678\project_44_12345678.cache\compile_simlib\modelsim (0, 2020-11-29)
project_44_12345678\project_44_12345678.cache\compile_simlib\questa (0, 2020-11-29)
project_44_12345678\project_44_12345678.cache\compile_simlib\riviera (0, 2020-11-29)
project_44_12345678\project_44_12345678.cache\compile_simlib\vcs (0, 2020-11-29)
project_44_12345678\project_44_12345678.cache\compile_simlib\xcelium (0, 2020-11-29)
project_44_12345678\project_44_12345678.cache\ip (0, 2020-11-29)
project_44_12345678\project_44_12345678.cache\ip\2017.4 (0, 2020-11-29)
project_44_12345678\project_44_12345678.cache\wt (0, 2020-10-16)
project_44_12345678\project_44_12345678.cache\wt\gui_handlers.wdf (14678, 2020-11-29)
project_44_12345678\project_44_12345678.cache\wt\java_command_handlers.wdf (3722, 2020-11-29)
project_44_12345678\project_44_12345678.cache\wt\project.wpc (123, 2020-11-29)
project_44_12345678\project_44_12345678.cache\wt\synthesis.wdf (5380, 2020-11-29)
project_44_12345678\project_44_12345678.cache\wt\synthesis_details.wdf (100, 2020-11-29)
project_44_12345678\project_44_12345678.cache\wt\webtalk_pa.xml (12222, 2020-11-29)
project_44_12345678\project_44_12345678.cache\wt\xsim.wdf (256, 2020-10-16)
project_44_12345678\project_44_12345678.hw (0, 2020-11-29)
project_44_12345678\project_44_12345678.hw\hw_1 (0, 2020-10-14)
project_44_12345678\project_44_12345678.hw\hw_1\hw.xml (1583, 2020-11-29)
project_44_12345678\project_44_12345678.hw\hw_1\wave (0, 2020-11-29)
project_44_12345678\project_44_12345678.hw\project_44_12345678.lpr (343, 2020-10-14)
project_44_12345678\project_44_12345678.ip_user_files (0, 2020-11-29)
project_44_12345678\project_44_12345678.runs (0, 2020-11-29)
project_44_12345678\project_44_12345678.runs\.jobs (0, 2020-11-29)
project_44_12345678\project_44_12345678.runs\.jobs\vrs_config_1.xml (441, 2020-10-14)
project_44_12345678\project_44_12345678.runs\.jobs\vrs_config_10.xml (441, 2020-10-14)
project_44_12345678\project_44_12345678.runs\.jobs\vrs_config_11.xml (438, 2020-10-16)
project_44_12345678\project_44_12345678.runs\.jobs\vrs_config_12.xml (248, 2020-10-16)
project_44_12345678\project_44_12345678.runs\.jobs\vrs_config_13.xml (441, 2020-10-16)
project_44_12345678\project_44_12345678.runs\.jobs\vrs_config_14.xml (441, 2020-10-16)
... ...
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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