Low-Cost-and-Programmable-CRC
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：12468KB
下载次数：0
上传日期：2021-01-08 07:05:45
上 传 者：
sh-1993
说明： 论文源代码“基于FPGA的低成本可编程CRC实现”
(Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA")
文件列表:
Parallel CRC implementation (0, 2020-05-01)
Parallel CRC implementation\MATLAB (0, 2020-05-01)
Parallel CRC implementation\MATLAB\W_ln_computation.m (2408, 2020-05-01)
Parallel CRC implementation\MATLAB\n_power_of_T.m (2253, 2020-05-01)
Pipelining go back algorithm (0, 2020-05-01)
Pipelining go back algorithm\MATLAB (0, 2020-05-01)
Pipelining go back algorithm\MATLAB\crc_go_back_new.m (2235, 2020-05-01)
Pipelining go back algorithm\MATLAB\formatrix_new.m (2530, 2020-05-01)
Pipelining go back algorithm\Verilog (0, 2020-05-01)
Pipelining go back algorithm\Verilog\go_back_pipe.v (101268, 2020-05-01)
Pipelining go back algorithm\Verilog\go_back_stage.v (4982, 2020-05-01)
Pipelining go back algorithm\Verilog\lut_xor.v (1968, 2020-05-01)
Reprogramming by HWICAP (0, 2020-05-01)
Reprogramming by HWICAP\Python (0, 2020-05-01)
Reprogramming by HWICAP\Python\lut_pin_map.py (452, 2020-05-01)
Reprogramming by HWICAP\Python\map_SliceL.py (999, 2020-05-01)
Reprogramming by HWICAP\Python\map_SliceM.py (520, 2020-05-01)
Reprogramming by HWICAP\Python\rbt_translation.py (744, 2020-05-01)
Reprogramming by HWICAP\TCL (0, 2020-05-01)
Reprogramming by HWICAP\TCL\Read (0, 2020-05-01)
Reprogramming by HWICAP\TCL\Read\read_frame_510521.tcl (3932, 2020-05-01)
Reprogramming by HWICAP\TCL\Read\read_frame_510622.tcl (3933, 2020-05-01)
Reprogramming by HWICAP\TCL\Read\read_frame_510723.tcl (3932, 2020-05-01)
Reprogramming by HWICAP\TCL\Read\read_frame_510824.tcl (3932, 2020-05-01)
Reprogramming by HWICAP\TCL\Write (0, 2020-05-01)
Reprogramming by HWICAP\TCL\Write\source_write_all.tcl (416, 2020-05-01)
Reprogramming by HWICAP\TCL\Write\write_frame_510521.tcl (3825, 2020-05-01)
Reprogramming by HWICAP\TCL\Write\write_frame_510622.tcl (3826, 2020-05-01)
Reprogramming by HWICAP\TCL\Write\write_frame_510723.tcl (3825, 2020-05-01)
Reprogramming by HWICAP\TCL\Write\write_frame_510824.tcl (3825, 2020-05-01)
Reprogramming by HWICAP\Verilog (0, 2020-05-01)
Reprogramming by HWICAP\Verilog\cnt.v (1594, 2020-05-01)
Reprogramming by HWICAP\Verilog\ipcores (0, 2020-05-01)
Reprogramming by HWICAP\Verilog\ipcores\axi_hwicap_0.xci (7729, 2020-05-01)
Reprogramming by HWICAP\Verilog\ipcores\clk_wiz_0.xci (81204, 2020-05-01)
Reprogramming by HWICAP\Verilog\ipcores\ila_0.xci (402544, 2020-05-01)
... ...
# Low-Cost-and-High-Perf-CRC
Two algorithms and a method are given here to implement a low-cost and high performance CRC. The ethernet CRC32 is used here, because it is the most used CRC. The design is developed by verilog and it is verified in VC709 FPGA board. More information can be founded in paper "Low-Cost and Programmable CRC Implementation based on FPGA".
## Parallel CRC implementation
The matlab codes are developed for the computation of matrix T^n and matrix W(l,n), which are used in equation (5) of paper "Low-Cost and Programmable CRC Implementation based on FPGA".
## Stride-by-5 algorithm
The stride-by-5 algorithm make full use of 5-inputs LUTs in Xilinx FPGAs. Matlab codes are developed for the initial value of LUTs. These matlab codes are based on the results of the previous matlab codes, which are used to compute T^n and W(l,n). Verilog codes for the stride-by-5 algorithm and the xor tree are developed, and they are verified on VC709 FPGA board.
## Pipelining go back algorithm
The algorithm is used to solve the final beat problem, which is descriped in the paper. The overhead can achieve an O(log(n)) overhead. Matlab codes are developed for the computation of matrix T^(-n). These computation are based on GF(2). Another matlab code is developed for the translation from matrix T^(-n) to the initial value of LUTs. Verilog codes are developed, and they are verified on VC709 FPGA board.
## Reprogramming by HWICAP
This method is least described in the paper but most described here. As far as we know, this is the
first open source code covering the whole procedure of programming a single LUT. A complete procedure is described in the document, and the code(including tcl, python and verilog) are given here.
## Segmented Architecture
The source code of proprsed segmented architecture can be accessed here. After adding the verilog source files in this folder to Modelsim, we can run a simulation.
## Test result
The synthesis result, which is present as a vivado synthesis report is given here. The LUTs consumption and frequency can be founded. The throughput of segmented architecture on various frame length (***bytes to 1518 bytes) can be founded.
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