DAC-Waveform-Moving-Block-Verilog
所属分类：VHDL/FPGA/Verilog
开发工具：SystemVerilog
文件大小：1461KB
下载次数：0
上传日期：2021-03-09 19:08:04
上 传 者：
sh-1993
说明： DAC波形移动块Verilog，，
(DAC-Waveform-Moving-Block-Verilog,,)
文件列表:
project_3 (0, 2021-03-10)
project_3\lab3_tb_behav.wcfg (3439, 2021-03-10)
project_3\project_3.cache (0, 2021-03-10)
project_3\project_3.cache\wt (0, 2021-03-10)
project_3\project_3.cache\wt\gui_handlers.wdf (12354, 2021-03-10)
project_3\project_3.cache\wt\java_command_handlers.wdf (3231, 2021-03-10)
project_3\project_3.cache\wt\project.wpc (123, 2021-03-10)
project_3\project_3.cache\wt\synthesis.wdf (5389, 2021-03-10)
project_3\project_3.cache\wt\synthesis_details.wdf (100, 2021-03-10)
project_3\project_3.cache\wt\webtalk_pa.xml (10541, 2021-03-10)
project_3\project_3.cache\wt\xsim.wdf (235, 2021-03-10)
project_3\project_3.hw (0, 2021-03-10)
project_3\project_3.hw\hw_1 (0, 2021-03-10)
project_3\project_3.hw\hw_1\hw.xml (1594, 2021-03-10)
project_3\project_3.hw\project_3.lpr (343, 2021-03-10)
project_3\project_3.hw\webtalk (0, 2021-03-10)
project_3\project_3.hw\webtalk\.xsim_webtallk.info (54, 2021-03-10)
project_3\project_3.hw\webtalk\labtool_webtalk.log (693, 2021-03-10)
project_3\project_3.hw\webtalk\usage_statistics_ext_labtool.html (2913, 2021-03-10)
project_3\project_3.hw\webtalk\usage_statistics_ext_labtool.xml (2521, 2021-03-10)
project_3\project_3.ip_user_files (0, 2021-03-10)
project_3\project_3.ip_user_files\ip (0, 2021-03-10)
project_3\project_3.ip_user_files\ip\clk_wiz_0 (0, 2021-03-10)
project_3\project_3.ip_user_files\ip\clk_wiz_0\clk_wiz_0.veo (3758, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts (0, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts\clk_wiz_0 (0, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts\clk_wiz_0\activehdl (0, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts\clk_wiz_0\activehdl\clk_wiz_0.sh (4927, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts\clk_wiz_0\activehdl\clk_wiz_0.udo (0, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts\clk_wiz_0\activehdl\compile.do (361, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts\clk_wiz_0\activehdl\file_info.txt (356, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts\clk_wiz_0\activehdl\glbl.v (1474, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts\clk_wiz_0\activehdl\simulate.do (299, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts\clk_wiz_0\activehdl\wave.do (32, 2021-03-10)
project_3\project_3.ip_user_files\sim_scripts\clk_wiz_0\ies (0, 2021-03-10)
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# DAC Waveform and Moving Block
This project uses a DAC module to create an analog waveform and the VGA
controller to generate a moving block. I also use the seven segment display
module from a previous project for testing and display.
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