41_eth_ddr3_lcd
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：9441KB
下载次数：1
上传日期：2021-03-21 00:33:00
上 传 者：
哈哈你你
说明： “基于 ROM 的 LCD图片显示实验 ”中利用 FPGA 片上存储资源存储图片，并通过 LCD接口将图片显示到 LCD屏幕上。但是由于 FPGA 片上存储资源有限，只能存储分辨率较小的图片
(In the experiment of LCD image display based on ROM, FPGA on-chip storage resources are used to store pictures, and the pictures are displayed on LCD screen through LCD interface. However, due to the limited on-chip memory resources of FPGA, it can only store images with smaller resolution)
文件列表:
doc (0, 2021-01-29)
doc\fengjing.bin (768000, 2018-06-27)
doc\风景.jpg (84521, 2018-06-27)
prj (0, 2021-01-29)
prj\eth_ddr3_lcd.ucf (12293, 2021-01-26)
prj\eth_ddr3_lcd (0, 2021-01-29)
prj\eth_ddr3_lcd\_ngo (0, 2021-01-29)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro (0, 2021-01-29)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\_xmsgs (0, 2021-01-29)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\_xmsgs\xst.xmsgs (27551, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\coregen.cgc (16250, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\coregen.cgp (520, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\coregen.log (2535, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\generate_icon_pro.xco (684, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\icon_pro.gise (1167, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\icon_pro.ucf (375, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\icon_pro.vhd (947, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\icon_pro.vho (1366, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\icon_pro.xco (1660, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\icon_pro.xise (41251, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\icon_pro_flist.txt (199, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\icon_pro_xmdf.tcl (2504, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\tmp (0, 2021-01-29)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\tmp\_cg (0, 2021-01-28)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\tmp\_xmsgs (0, 2021-01-29)
prj\eth_ddr3_lcd\_ngo\cs_icon_pro\tmp\_xmsgs\pn_parser.xmsgs (807, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0 (0, 2021-01-29)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\_xmsgs (0, 2021-01-29)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\_xmsgs\xst.xmsgs (29843, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\coregen.cgc (43910, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\coregen.cgp (520, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\coregen.log (2559, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\generate_ila_pro_0.xco (3184, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\ila_pro_0.cdc (1620, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\ila_pro_0.gise (1169, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\ila_pro_0.ucf (424, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\ila_pro_0.vhd (1022, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\ila_pro_0.vho (1475, 2020-12-08)
prj\eth_ddr3_lcd\_ngo\cs_ila_pro_0\ila_pro_0.xco (4221, 2020-12-08)
... ...
The design files are located at
E:/sp6/chaoyuez/ddr_rw/top_ddr3_rw/prj/top_ddr3_rw/ipcore_dir:
- ddr3.veo:
veo template file containing code that can be used as a model
for instantiating a CORE Generator module in a HDL design.
- ddr3.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
- ddr3_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
- ddr3_readme.txt:
Text file indicating the files generated and how they are used.
- ddr3_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
- ddr3.gise and ddr3.xise:
ISE Project Navigator support files. These are generated files and
should not be edited directly.
- ddr3 directory.
In the ddr3 directory, three folders are created:
- docs:
This folder contains Virtex-6 FPGA Memory Interface Solutions user guide
and data sheet.
- example_design:
This folder includes the design with synthesizable test bench.
- user_design:
This folder includes the design without test bench modules.
The example_design and user_design folders contain several other folders
and files. All these output folders are discussed in more detail in
Spartan-6 FPGA Memory Controller user guide (ug388.pdf) located in docs folder.
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