class10_HEX8
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：485KB
下载次数：0
上传日期：2021-04-02 19:11:33
上 传 者：
勿恋影中人
说明： 数码管的时序控制程序，基于FPGA并行设计平台，入门级设计
(Digital tube timing control program, based on FPGA parallel design platform, entry level design)
文件列表:
class10_HEX8\doc\8位7段数码管驱动实验.docx (445429, 2015-09-03)
class10_HEX8\doc\单个数码管模型.vsdx (20505, 2015-08-31)
class10_HEX8\doc\数码管驱动模块原理图.vsdx (26411, 2015-08-31)
class10_HEX8\prj\HXE8.qpf (1273, 2015-08-31)
class10_HEX8\prj\HXE8.qsf (4817, 2015-12-09)
class10_HEX8\prj\HXE8.qws (613, 2015-12-09)
class10_HEX8\prj\ip\greybox_tmp\cbx_args.txt (221, 2015-08-31)
class10_HEX8\prj\ip\hex_data.qip (301, 2015-08-31)
class10_HEX8\prj\ip\hex_data.v (3973, 2015-08-31)
class10_HEX8\prj\ip\hex_data_bb.v (2930, 2015-08-31)
class10_HEX8\prj\output_files\HXE8.done (26, 2015-12-09)
class10_HEX8\prj\output_files\HXE8.fit.smsg (703, 2015-12-09)
class10_HEX8\prj\output_files\HXE8.fit.summary (609, 2015-12-09)
class10_HEX8\prj\output_files\HXE8.jdi (5177, 2015-12-09)
class10_HEX8\prj\output_files\HXE8.map.summary (469, 2015-12-09)
class10_HEX8\prj\output_files\HXE8.pin (33040, 2015-12-09)
class10_HEX8\prj\output_files\HXE8.sof (359214, 2015-12-09)
class10_HEX8\prj\output_files\HXE8.sta.summary (1641, 2015-12-09)
class10_HEX8\prj\Spf2.spf (5132, 2015-08-31)
class10_HEX8\rtl\HXE8.v (2047, 2015-08-31)
class10_HEX8\rtl\HXE_top.v (448, 2015-08-31)
class10_HEX8\testbench\HXE_tb.v (757, 2015-08-31)
class10_HEX8\文件夹模版.txt (216, 2015-07-19)
class10_HEX8\prj\ip\greybox_tmp (0, 2015-08-31)
class10_HEX8\prj\ip (0, 2015-08-31)
class10_HEX8\prj\output_files (0, 2015-12-14)
class10_HEX8\doc (0, 2015-09-30)
class10_HEX8\img (0, 2015-06-29)
class10_HEX8\prj (0, 2015-12-14)
class10_HEX8\rtl (0, 2015-12-14)
class10_HEX8\testbench (0, 2015-12-14)
class10_HEX8 (0, 2015-08-31)
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