I2C_wr(no-down)
i2c 

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:1071KB
下载次数:7
上传日期:2011-08-08 22:36:34
上 传 者michelle1991
说明:  I2C的读写时序,希望有帮助,写的很辛苦当时
(I2C read and write timing, want to help, write a very hard time)

文件列表:
I2C_wr(no down)\test_isim_beh.exe (90112, 2011-08-03)
I2C_wr(no down)\I2Cwr3.xise (33898, 2011-08-06)
I2C_wr(no down)\isim\precompiled.exe.sim\std\textio.didat (2368, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_0774719531.didat (2120, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_2592010699.didat (5664, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_4165608084.didat (4604, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_1367372525.didat (15964, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_3972351953.didat (8004, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_3499444699.didat (4232, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_3039841270.didat (5400, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_1242562249.didat (8376, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_3564397177.didat (4624, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_2717149903.didat (12072, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_0017514958.didat (3620, 2011-08-03)
I2C_wr(no down)\isim\precompiled.exe.sim\ieee\p_3620187407.didat (2232, 2011-08-03)
I2C_wr(no down)\isim\isim_usage_statistics.html (1684, 2011-08-03)
I2C_wr(no down)\isim\work\mi.vdb (10314, 2011-08-03)
I2C_wr(no down)\isim\work\test.vdb (2860, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\p_0947159679.didat (5108, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\p_0947159679.c (1203, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\p_3222816464.didat (15820, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\p_3222816464.c (188183, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_2936104250_2014779070.didat (3688, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_2936104250_2014779070.c (17353, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_4002211264_2683070183.didat (4092, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_4002211264_2683070183.c (9587, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_1692151727_2982649196.didat (3572, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_1692151727_2982649196.c (7910, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_1717487767_2982649196.didat (3572, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_1717487767_2982649196.c (7914, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_0402065255_2679555531.didat (6084, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_0402065255_2679555531.c (20721, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_1001209034_1233898481.didat (55184, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_1001209034_1233898481.c (264955, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_1490675510_1976025627.didat (2484, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_1490675510_1976025627.c (2134, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\p_0947159679.nt.obj (612, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_2936104250_2014779070.nt.obj (2172, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\a_4002211264_2683070183.nt.obj (2822, 2011-08-03)
I2C_wr(no down)\isim\test_isim_beh.exe.sim\unisim\p_3222816464.nt.obj (51497, 2011-08-03)
... ...

The following files were generated for 'icon_pro' in directory D:\FPGA\I2C\I2Cwr(no down)\_ngo\cs_icon_pro\ icon_pro.gise: ISE Project Navigator support file. This is a generated file and should not be edited directly. icon_pro.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. icon_pro.vhd: Unisim VHDL file containing the information required to simulate the module. icon_pro.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. icon_pro.xco: CORE Generator input file containing the parameters used to regenerate a core. icon_pro.xise: ISE Project Navigator support file. This is a generated file and should not be edited directly. icon_pro_readme.txt: Text file indicating the files generated and how they are used. icon_pro_xmdf.tcl: ISE Project Navigator interface file. ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project. icon_pro_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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