FPGA_test_demo
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：8060KB
下载次数：0
上传日期：2021-04-09 15:56:16
上 传 者：
hehehe123456
说明： fpga常用的经典例程，可供小白快速入门，帮助极大
(FPGA commonly used classic routines, for white quick start, great help)
文件列表:
FPGA_test_demo\db (0, 2020-06-23)
FPGA_test_demo\db\.cmp.kpt (201, 2020-06-23)
FPGA_test_demo\db\prev_cmp_top.qmsg (4613, 2020-06-23)
FPGA_test_demo\db\top.(0).cnf.cdb (1986, 2020-06-23)
FPGA_test_demo\db\top.(0).cnf.hdb (1184, 2020-06-23)
FPGA_test_demo\db\top.(1).cnf.cdb (2019, 2020-06-23)
FPGA_test_demo\db\top.(1).cnf.hdb (858, 2020-06-23)
FPGA_test_demo\db\top.(2).cnf.cdb (2901, 2020-06-23)
FPGA_test_demo\db\top.(2).cnf.hdb (1159, 2020-06-23)
FPGA_test_demo\db\top.(3).cnf.cdb (6750, 2020-06-23)
FPGA_test_demo\db\top.(3).cnf.hdb (2644, 2020-06-23)
FPGA_test_demo\db\top.asm.qmsg (2469, 2020-06-23)
FPGA_test_demo\db\top.asm.rdb (775, 2020-06-23)
FPGA_test_demo\db\top.asm_labs.ddb (30890, 2020-06-23)
FPGA_test_demo\db\top.cbx.xml (85, 2020-06-23)
FPGA_test_demo\db\top.cmp.bpm (852, 2020-06-23)
FPGA_test_demo\db\top.cmp.cdb (29810, 2020-06-23)
FPGA_test_demo\db\top.cmp.hdb (16069, 2020-06-23)
FPGA_test_demo\db\top.cmp.idb (2362, 2020-06-23)
FPGA_test_demo\db\top.cmp.logdb (18668, 2020-06-23)
FPGA_test_demo\db\top.cmp.rdb (26498, 2020-06-23)
FPGA_test_demo\db\top.cmp_merge.kpt (207, 2020-06-23)
FPGA_test_demo\db\top.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd (746217, 2020-06-23)
FPGA_test_demo\db\top.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd (739602, 2020-06-23)
FPGA_test_demo\db\top.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd (740761, 2020-06-23)
FPGA_test_demo\db\top.db_info (139, 2020-06-23)
FPGA_test_demo\db\top.eda.qmsg (4975, 2020-06-23)
FPGA_test_demo\db\top.fit.qmsg (26845, 2020-06-23)
FPGA_test_demo\db\top.hier_info (5230, 2020-06-23)
FPGA_test_demo\db\top.hif (596, 2020-06-23)
FPGA_test_demo\db\top.logic_util_heuristic.dat (11396, 2020-06-23)
FPGA_test_demo\db\top.lpc.html (990, 2020-06-23)
FPGA_test_demo\db\top.lpc.rdb (502, 2020-06-23)
FPGA_test_demo\db\top.lpc.txt (1935, 2020-06-23)
FPGA_test_demo\db\top.map.ammdb (128, 2020-06-23)
FPGA_test_demo\db\top.map.bpm (812, 2020-06-23)
FPGA_test_demo\db\top.map.cdb (10235, 2020-06-23)
FPGA_test_demo\db\top.map.hdb (15377, 2020-06-23)
FPGA_test_demo\db\top.map.kpt (1567, 2020-06-23)
FPGA_test_demo\db\top.map.logdb (4, 2020-06-23)
... ...
三个子模块在【SubModule】文件夹内
(注意:编译前建议一定要【右键top】指定好的【项目设置】文件路径)
编译完后,【Programmer】进入程序烧录窗口, 【Add files】添加烧录文件top.sof(在【output_files】文件夹), 最后点击【Start】就完成了,实验箱看效果
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