verilog_code
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：54KB
下载次数：0
上传日期：2021-04-11 20:36:43
上 传 者：
xzren_123
说明： 在FPGA或者数字IC前端设计中，经常会使用异步FIFO设计实现多bit数据的跨时钟域，但是FIFO的难点应该改是在于怎样判断FIFO的空/满状态以保证数据的安全性。为了在项目中保证FIFO数据正确的读写，不让FIFO出现读空或者写满的状态，除了保证FIFO的地址空间的大小，还需要利用read_empty、write_full保证数据安全。怎样判断FIFO的满/空就成了FIFO设计的核心问题。由于是连续变化的数据，因此可以使用格雷码实现不同时钟域下读写指针的传递，最终实现read_empty、write_full的控制。
(In FPGA or digital IC front-end design, asynchronous FIFO design is often used to realize multi bit data cross clock domain, but the difficulty of FIFO should be how to judge the empty / full state of FIFO to ensure data security. In order to ensure the correct reading and writing of FIFO data in the project and prevent the FIFO from reading empty or writing full, in addition to ensuring the size of FIFO address space,read is also needed_ empty,write_ Full ensures data security. How to judge the FIFO full / empty has become the core problem of FIFO design. Due to the continuous change of data, gray code can be used to achieve the transfer of read-write pointer in different clock domains, and finally achieve read_ empty,write_ Full control.)
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