ov7670-master
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：50KB
下载次数：0
上传日期：2021-04-15 01:44:49
上 传 者：
Thanh Phuc
说明： ov-7670 master verilog
文件列表:
baud_gen_uart.v (345, 2018-09-19)
captured_images (0, 2018-09-19)
captured_images\cross.pgm (19214, 2018-09-19)
captured_images\hello.pgm (19214, 2018-09-19)
captured_images\thank_you.pgm (19214, 2018-09-19)
frame_cap.v (1388, 2018-09-19)
fsm.v (1500, 2018-09-19)
i2c.v (3660, 2018-09-19)
i2c_clk.v (435, 2018-09-19)
ov7670_registers.v (707, 2018-09-19)
top.v (2668, 2018-09-19)
uart_tx.v (1305, 2018-09-19)
ucf.ucf (2403, 2018-09-19)
# ov7670
Verilog Implementation to capture a frame from ov7670 camera module.
The project was implemented on Numato MimasV2 FPGA Board. Due to Block Ram limitations , a 160x120 frame is captured in YUV format.
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