DDS_top
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：4206KB
下载次数：0
上传日期：2021-04-19 09:23:50
上 传 者：
SeeJaedong
说明： 使用verilog语言，实现dds信号发生器的源代码
(use dds to generate chirp signal)
文件列表:
DDS_top\DDS_top\DDS_top.bld (1044, 2019-06-25)
DDS_top\DDS_top\DDS_top.cmd_log (2073, 2019-06-25)
DDS_top\DDS_top\DDS_top.gise (13474, 2019-06-25)
DDS_top\DDS_top\DDS_top.lso (6, 2019-06-25)
DDS_top\DDS_top\DDS_top.ncd (91357, 2019-06-25)
DDS_top\DDS_top\DDS_top.ngc (11977, 2019-06-25)
DDS_top\DDS_top\DDS_top.ngd (197202, 2019-06-25)
DDS_top\DDS_top\DDS_top.ngr (6164, 2019-06-25)
DDS_top\DDS_top\DDS_top.pad (13490, 2019-06-25)
DDS_top\DDS_top\DDS_top.par (8231, 2019-06-25)
DDS_top\DDS_top\DDS_top.pcf (221, 2019-06-25)
DDS_top\DDS_top\DDS_top.prj (62, 2019-06-25)
DDS_top\DDS_top\DDS_top.ptwx (17226, 2019-06-25)
DDS_top\DDS_top\DDS_top.stx (0, 2019-06-25)
DDS_top\DDS_top\DDS_top.syr (14653, 2019-06-25)
DDS_top\DDS_top\DDS_top.twr (9226, 2019-06-25)
DDS_top\DDS_top\DDS_top.twx (31936, 2019-06-25)
DDS_top\DDS_top\DDS_top.unroutes (161, 2019-06-25)
DDS_top\DDS_top\DDS_top.v (1145, 2019-06-25)
DDS_top\DDS_top\DDS_top.xise (36696, 2019-06-24)
DDS_top\DDS_top\DDS_top.xpi (46, 2019-06-25)
DDS_top\DDS_top\DDS_top.xst (1093, 2019-06-25)
DDS_top\DDS_top\DDS_top_envsettings.html (17463, 2019-06-25)
DDS_top\DDS_top\DDS_top_guide.ncd (91357, 2019-06-25)
DDS_top\DDS_top\DDS_top_map.map (7181, 2019-06-25)
DDS_top\DDS_top\DDS_top_map.mrp (19735, 2019-06-25)
DDS_top\DDS_top\DDS_top_map.ncd (52658, 2019-06-25)
DDS_top\DDS_top\DDS_top_map.ngm (361866, 2019-06-25)
DDS_top\DDS_top\DDS_top_map.xrpt (47513, 2019-06-25)
DDS_top\DDS_top\DDS_top_ngdbuild.xrpt (9157, 2019-06-25)
DDS_top\DDS_top\DDS_top_pad.csv (13522, 2019-06-25)
DDS_top\DDS_top\DDS_top_pad.txt (52300, 2019-06-25)
DDS_top\DDS_top\DDS_top_par.xrpt (156532, 2019-06-25)
DDS_top\DDS_top\DDS_top_summary.html (17453, 2019-06-25)
DDS_top\DDS_top\DDS_top_summary.xml (408, 2019-06-25)
DDS_top\DDS_top\DDS_top_tb.fdo (1336, 2019-06-25)
DDS_top\DDS_top\DDS_top_tb.udo (383, 2019-06-22)
DDS_top\DDS_top\DDS_top_tb.v (1187, 2019-06-25)
DDS_top\DDS_top\DDS_top_tb.v.bak (1178, 2019-06-22)
DDS_top\DDS_top\DDS_top_tb_wave.fdo (428, 2019-06-22)
... ...
The following files were generated for 'dds_ip' in directory
D:\ISE_FPGA_Project\liruifeng_tem\ISE_learning\DDS_top\DDS_top\ipcore_dir\
Generate XCO file:
CORE Generator input file containing the parameters used to generate a core.
* dds_ip.xco
Generate Implementation Netlist:
Binary Xilinx implementation netlist files containing the information
required to implement the module in a Xilinx (R) FPGA.
* dds_ip.ngc
Obfuscate Netlist Generator:
Please see the core data sheet.
* dds_ip.ngc
Generate Instantiation Templates:
Template files containing code that can be used as a model for instantiating
a CORE Generator module in an HDL design.
* dds_ip.veo
RTL Simulation Model Generator:
Please see the core data sheet.
* dds_ip.v
All Documents Generator:
Please see the core data sheet.
* dds_ip/doc/dds_compiler_v4_0_vinfo.html
* dds_ip/doc/dds_ds558.pdf
Deliver IP Symbol:
Graphical symbol information file. Used by the ISE tools and some third party
tools to create a symbol representing the core.
* dds_ip.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* dds_ip.sym
Generate XMDF file:
ISE Project Navigator interface file. ISE uses this file to determine how the
files output by CORE Generator for the core can be integrated into your ISE
project.
* dds_ip_xmdf.tcl
Generate ISE project file:
ISE Project Navigator support files. These are generated files and should not
be edited directly.
* _xmsgs/pn_parser.xmsgs
* dds_ip.gise
* dds_ip.xise
Deliver Readme:
Readme file for the IP.
* dds_ip_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* dds_ip_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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