文件列表:

source (0, 2021-04-16)
source\farrow.sv (1490, 2020-04-20)
source\fir_tap.sv (1289, 2020-04-20)
source\fractional_offset.sv (1345, 2020-04-20)
source\poly_stage.sv (1645, 2020-04-20)
source\systolic_fir.sv (912, 2020-04-20)
source\systolic_poly.sv (1621, 2020-04-20)
test_bench (0, 2021-04-16)
test_bench\farrow_glitch_tb.sv (2304, 2020-04-20)
test_bench\farrow_tb.sv (2287, 2020-04-20)
test_bench\fractional_offset.sv (527, 2020-04-20)
test_bench\fractional_offset_tb.sv (926, 2020-04-20)
test_bench\poly_fit.sv (4763, 2020-04-20)
test_bench\poly_fit_tb.sv (1165, 2020-04-20)
test_bench\qr_decomposition.sv (3182, 2020-04-20)
test_bench\qr_decomposition_tb.sv (1245, 2020-04-20)
test_bench\sinc_filter_matrix.sv (1329, 2020-04-20)
test_bench\sinc_filter_matrix_tb.sv (745, 2020-04-20)
test_bench\sinc_filter_poly_matrix.sv (1340, 2020-04-20)
test_bench\sinc_filter_poly_matrix_tb.sv (812, 2020-04-20)
test_bench\sinc_tb.sv (651, 2020-04-20)
test_bench\solve_triangular.sv (1158, 2020-04-20)
test_bench\solve_triangular_tb.sv (1329, 2020-04-20)
test_bench\systolic_poly_tb.sv (1621, 2020-04-20)

# VerilogFarrowFilter Fractional interpolation using a Farrow structure *** Some modules needed for this project for lower level functions are provided in VerilogCommon project. Those files are not repeated here. This project is a high level demonstration of interpolation using a Farrow structure. farrow_tb.sv Use this top file to demonstrate filter operation. If the x and y input and output are shown in analog set to hold values between clocks, the interpolation can clearly be seen. The FIR filters and polynomial filter are working correctly. Currently, the time offset from the input clock to the current point is just set by an incrementing step based on the output clock. Although this works in the above example, this is not a robust method of calculating the offset from the input clock. I have included another test bench to demonstrate this: farrow_glitch_tb.sv This file changes the time step from 1/4 to 3/7. When the simulation is run, you will see that a step outside of the input waveform is generated about every 7 clock cycles. Although this can be corrected by adjusting the offset between the input and output clocks in the test bench (change repeat value in repeat(1) @(posedge clkOut); in clkIn generator block) this is obviously not a robust way to generate the timing offset variable. I expect a more robust solution would be based on both clock inputs. The offset value (t in the farrow module) could be changed to an input to that module. If both clocks are generated by the same structure in an implementation, there may be other signals provided that simplify the correct calculation. The testbench directory includes several files that generate a matrix of sinc values and then creates a smaller matrix of polynomial fits to the sinc values. Since these values use verilog DPI c functions to do the calculation, they are not synthesizable. It is assumed that an implementaion would provide constants for this purpose. The code was included to prvide an easy way to change the parameters during the design process.

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