20_hs_ad_da
所属分类：VHDL/FPGA/Verilog
开发工具：Vivado
文件大小：44369KB
下载次数：7
上传日期：2021-04-28 08:55:24
上 传 者：
7122529
说明： Verilog语言，基于赛灵思的A7-100T.高速AD 转换芯片和高速DA 转换芯片分别是AD9280 和AD9708。FPGA 产生正弦波变化的数字信号，经过DA 芯片后转换成模拟信号，将DA 的模拟电压输出端连接至AD 的模拟电压输入端，AD 芯片将模拟信号转换成数字信号，然后通过ILA 观察数字信号的波形是否按照正弦波波形变化。
(The FPGA generates a digital signal with sine wave variation and converts it into an analog signal after passing through the DA chip, and connects the analog voltage output of the DA to the analog voltage input of the AD. The AD chip converts the analog signal into a digital signal, and then observes whether the waveform of the digital signal changes according to the sine waveform through the ILA.)
文件列表:
20_hs_ad_da (0, 2021-03-10)
20_hs_ad_da\doc (0, 2021-03-10)
20_hs_ad_da\doc\dds_256x8b_wave.coe (1348, 2020-08-04)
20_hs_ad_da\hs_ad_da.cache (0, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\compile_simlib (0, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\compile_simlib\activehdl (0, 2021-04-01)
20_hs_ad_da\hs_ad_da.cache\compile_simlib\ies (0, 2021-04-01)
20_hs_ad_da\hs_ad_da.cache\compile_simlib\modelsim (0, 2021-04-01)
20_hs_ad_da\hs_ad_da.cache\compile_simlib\questa (0, 2021-04-01)
20_hs_ad_da\hs_ad_da.cache\compile_simlib\riviera (0, 2021-04-01)
20_hs_ad_da\hs_ad_da.cache\compile_simlib\vcs (0, 2021-04-01)
20_hs_ad_da\hs_ad_da.cache\compile_simlib\xcelium (0, 2021-04-01)
20_hs_ad_da\hs_ad_da.cache\ip (0, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2 (0, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\3d53995757f1fd2d (0, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\3d53995757f1fd2d\3d53995757f1fd2d.xci (13044, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\3d53995757f1fd2d\rom_256x8b.dcp (27691, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\3d53995757f1fd2d\rom_256x8b_sim_netlist.v (29002, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\3d53995757f1fd2d\rom_256x8b_sim_netlist.vhdl (44998, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\3d53995757f1fd2d\rom_256x8b_stub.v (1333, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\3d53995757f1fd2d\rom_256x8b_stub.vhdl (1468, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\6864f2133fd3e80d (0, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\6864f2133fd3e80d\6864f2133fd3e80d.xci (7373, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\6864f2133fd3e80d\dbg_hub.dcp (358701, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\6864f2133fd3e80d\dbg_hub_sim_netlist.v (717121, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\6864f2133fd3e80d\dbg_hub_sim_netlist.vhdl (990117, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\6864f2133fd3e80d\dbg_hub_stub.v (1364, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\6864f2133fd3e80d\dbg_hub_stub.vhdl (1488, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\e135f9d3b389d499 (0, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\e135f9d3b389d499\dbg_hub.dcp (358616, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\e135f9d3b389d499\dbg_hub_sim_netlist.v (717120, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\e135f9d3b389d499\dbg_hub_sim_netlist.vhdl (990116, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\e135f9d3b389d499\dbg_hub_stub.v (1363, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\e135f9d3b389d499\dbg_hub_stub.vhdl (1487, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\e135f9d3b389d499\e135f9d3b389d499.xci (7372, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\fc8044e6abcd8504 (0, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\fc8044e6abcd8504\fc8044e6abcd8504.xci (398341, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\fc8044e6abcd8504\ila_0.dcp (592792, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\fc8044e6abcd8504\ila_0_sim_netlist.v (1491322, 2021-03-10)
20_hs_ad_da\hs_ad_da.cache\ip\2019.2\fc8044e6abcd8504\ila_0_sim_netlist.vhdl (3314106, 2021-03-10)
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