FlashROM
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3478KB
下载次数：35
上传日期：2011-08-18 16:42:37
上 传 者：
hfddm
说明： libero环境下FPGA中介绍ProASIC3/EFlash_ROM的仿真例程，
(libero FPGA environment described ProASIC3/EFlash_ROM simulation routines,)
文件列表:
FlashROM\FlashROM实验例程.pdf (2931347, 2007-11-13)
FlashROM\Flash_ROM\designer\impl1\designer.log (613, 2007-11-13)
FlashROM\Flash_ROM\designer\impl1\RDROM_top\projectData\RDROM_top.stp (70902, 2007-06-30)
FlashROM\Flash_ROM\designer\impl1\RDROM_top\RDROM_top.log (595, 2007-06-30)
FlashROM\Flash_ROM\designer\impl1\RDROM_top\RDROM_top.pro (2747, 2008-10-23)
FlashROM\Flash_ROM\designer\impl1\RDROM_top.adb (154624, 2007-06-30)
FlashROM\Flash_ROM\designer\impl1\RDROM_top.dtf\verify.log (233, 2007-06-30)
FlashROM\Flash_ROM\designer\impl1\RDROM_top.ide_des (881, 2008-10-23)
FlashROM\Flash_ROM\designer\impl1\RDROM_top.lok (426, 2008-10-23)
FlashROM\Flash_ROM\designer\impl1\RDROM_top.stp (70902, 2007-06-30)
FlashROM\Flash_ROM\designer\impl1\RDROM_top.tcl (175, 2008-10-23)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\@r@d@r@o@m_top\verilog.psm (96273, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\@r@d@r@o@m_top\_primary.dat (24916, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\@r@d@r@o@m_top\_primary.vhd (266, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\stimulus\verilog.psm (29923, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\stimulus\_primary.dat (2725, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\stimulus\_primary.vhd (221, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\tb_clock_minmax\verilog.psm (20175, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\tb_clock_minmax\_primary.dat (2231, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\tb_clock_minmax\_primary.vhd (837, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\testbench\verilog.psm (2329, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\testbench\_primary.dat (411, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\testbench\_primary.vhd (78, 2007-06-24)
FlashROM\Flash_ROM\designer\impl1\simulation\postlayout\_info (1481, 2007-06-24)
FlashROM\Flash_ROM\Flash_ROM.prj (6847, 2008-10-23)
FlashROM\Flash_ROM\hdl\ctrl_ROM.v (3089, 2007-06-20)
FlashROM\Flash_ROM\hdl\RDROM_top.v (2667, 2007-06-23)
FlashROM\Flash_ROM\hdl\send.v (2472, 2007-06-20)
FlashROM\Flash_ROM\hdl\Sim_top.v (841, 2007-06-22)
FlashROM\Flash_ROM\simulation\flashROM.mem (1280, 2007-11-13)
FlashROM\Flash_ROM\simulation\meminit.dat (2816, 2007-11-13)
FlashROM\Flash_ROM\simulation\modelsim.ini (343, 2008-10-23)
FlashROM\Flash_ROM\simulation\modelsim.ini.sav (308, 2007-11-13)
FlashROM\Flash_ROM\simulation\modelsim.log (4897, 2007-06-24)
FlashROM\Flash_ROM\simulation\presynth\@r@d@r@o@m_top\verilog.psm (5451, 2007-06-23)
FlashROM\Flash_ROM\simulation\presynth\@r@d@r@o@m_top\_primary.dat (600, 2007-06-23)
FlashROM\Flash_ROM\simulation\presynth\@r@d@r@o@m_top\_primary.vhd (347, 2007-06-23)
FlashROM\Flash_ROM\simulation\presynth\@sim_top\verilog.psm (5443, 2007-06-22)
FlashROM\Flash_ROM\simulation\presynth\@sim_top\_primary.dat (610, 2007-06-22)
FlashROM\Flash_ROM\simulation\presynth\@sim_top\_primary.vhd (343, 2007-06-22)
... ...
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