MCP2515-FPGA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3261KB
下载次数：2
上传日期：2021-07-08 15:57:25
上 传 者：
sh-1993
说明： 使用verilog语言完成状态机初始化MCP2515发送数据
(Using Verilog Language to Initialize State Machine MCP2515 and Send Data)
文件列表:
db (0, 2021-07-08)
db\.cmp.kpt (203, 2021-07-08)
db\altsyncram_0124.tdf (30143, 2021-07-08)
db\altsyncram_2124.tdf (54223, 2021-07-08)
db\altsyncram_2u14.tdf (15730, 2021-07-08)
db\altsyncram_4u14.tdf (16783, 2021-07-08)
db\altsyncram_6124.tdf (199616, 2021-07-08)
db\cmpr_ngc.tdf (1714, 2021-07-08)
db\cmpr_qgc.tdf (1946, 2021-07-08)
db\cmpr_rgc.tdf (2036, 2021-07-08)
db\cmpr_sgc.tdf (2106, 2021-07-08)
db\cntr_23j.tdf (3283, 2021-07-08)
db\cntr_9gi.tdf (3702, 2021-07-08)
db\cntr_agi.tdf (3702, 2021-07-08)
db\cntr_bbj.tdf (4432, 2021-07-08)
db\cntr_dgi.tdf (3828, 2021-07-08)
db\cntr_egi.tdf (3702, 2021-07-08)
db\cntr_gbj.tdf (4558, 2021-07-08)
db\cntr_i6j.tdf (3536, 2021-07-08)
db\cntr_igi.tdf (3954, 2021-07-08)
db\cntr_kgi.tdf (3828, 2021-07-08)
db\cntr_mcj.tdf (4811, 2021-07-08)
db\decode_bua.tdf (5471, 2021-07-08)
db\decode_dvf.tdf (1601, 2021-07-08)
db\decode_jsa.tdf (1544, 2021-07-08)
db\decode_msa.tdf (2293, 2021-07-08)
db\ip (0, 2021-07-08)
db\ip\sld6ed12f1a (0, 2021-07-08)
db\ip\sld6ed12f1a\alt_sld_fab.qip (13868, 2021-07-08)
db\ip\sld6ed12f1a\alt_sld_fab.sopcinfo (58796, 2021-07-08)
db\ip\sld6ed12f1a\alt_sld_fab.v (2416, 2021-07-08)
db\ip\sld6ed12f1a\alt_sld_fab__report.html (17692, 2021-07-08)
db\ip\sld6ed12f1a\alt_sld_fab__report.xml (27507, 2021-07-08)
db\ip\sld6ed12f1a\alt_sld_fab_wrapper_hw.tcl (3128, 2021-07-08)
db\ip\sld6ed12f1a\submodules (0, 2021-07-08)
db\ip\sld6ed12f1a\submodules\alt_sld_fab_alt_sld_fab.v (20752, 2021-07-08)
db\ip\sld6ed12f1a\submodules\alt_sld_fab_alt_sld_fab_ident.sv (3240, 2021-07-08)
db\ip\sld6ed12f1a\submodules\alt_sld_fab_alt_sld_fab_presplit.sv (576, 2021-07-08)
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