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MIPS-Pipelined-Processor

MIPS vhdl assembler computer-architecture mips-architecture

所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：202KB
下载次数：0
上传日期：2021-08-12 22:59:30
上传者：sh-1993

说明：这是一款哈佛架构的MIPS 5级32位流水线处理器，配有汇编程序来解释...
(This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.)

文件列表:

.vscode (0, 2021-08-13)
.vscode\tasks.json (1832, 2021-08-13)
Design.pdf (89932, 2021-08-13)
LICENSE (1068, 2021-08-13)
arch_img.png (85982, 2021-08-13)
assembler (0, 2021-08-13)
assembler\constants.py (1028, 2021-08-13)
assembler\helpers.py (2890, 2021-08-13)
assembler\main.py (3142, 2021-08-13)
do-files (0, 2021-08-13)
do-files\1-op.do (765, 2021-08-13)
do-files\2-op.do (1024, 2021-08-13)
do-files\FlagCalculator.do (831, 2021-08-13)
do-files\ForwadingUnit.do (745, 2021-08-13)
do-files\cpu.do (2818, 2021-08-13)
do-files\loaduse.do (781, 2021-08-13)
do-files\memory.do (1126, 2021-08-13)
do-files\test_control.do (584, 2021-08-13)
do-files\test_data_memory.do (637, 2021-08-13)
do-files\test_data_memory.mem (84, 2021-08-13)
do-files\test_fetch.do (1293, 2021-08-13)
do-files\test_fetch.mem (4, 2021-08-13)
do-files\test_instructions_memory.do (507, 2021-08-13)
do-files\test_instructions_memory.mem (84, 2021-08-13)
do-files\test_memory.do (1150, 2021-08-13)
memory-files (0, 2021-08-13)
memory-files\1-op.mem (425, 2021-08-13)
memory-files\2-op.mem (442, 2021-08-13)
memory-files\mem.mem (475, 2021-08-13)
src (0, 2021-08-13)
src\alu (0, 2021-08-13)
src\alu\ALU.vhd (2840, 2021-08-13)
src\alu\FlagCalculator.vhd (924, 2021-08-13)
src\alu\Full1bitAdder.vhd (272, 2021-08-13)
src\alu\FullnbitAdder.vhd (663, 2021-08-13)
src\cpu.vhd (7615, 2021-08-13)
src\general-components (0, 2021-08-13)
... ...

# MIPS 5 Stage Pipelined Processor #### This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes. #### ## Design

you can check the design here Design

## Features - Supports 8 registers from R1 to R7 - Supports Reset signal - Reading and writing to ports - Data hazard detection & handling using: - ALU-forwarding - Memory-forwarding - Stalling for load-use case - Control hazard detection & handling

## Stages - Fetch - Decode - Execute - Memory - Write Back ## IR format

Instruction Type	Immediate or register	Code	Rdest	Rsrc	Offset / Immediate value
31-30 (2 bits)	29 (1 bit)	28-24 (5 bits)	23-20 (4 bits)	19-16 (4 bits)	15-0 (16 bits)

## General components of an instruction opcode

0-operand or 1-operand	2-operands	Memory	Change of control
00	01	10	11

## Supported instructions

NO OP	One OP	Two OP	Memory
NOP	CLR	MOV	PUSH
SETC	NOT	ADD	POP
CLRC	INC	SUB	LDD
	NEG	AND	STD
	DEC	OR
	OUT	IADD
	IN	SHL
	RLC	SHR
	RRC	LDM

## Run * Write your program then run the assembler to convert it to binary file ``` python main.py ``` * Create your project in modelsim with a work library name. * Add all the .vhd files in [src](https://github.com/EmanOthman21/MIPS-Pipelined-Processor/blob/master/src) to the project. * Compile all files. * Then start simulation with cpu-arch * Make sure to change the directory of memory files in the do files before use them. ## Contributors

Bahaa Eldeen

Eman Othman

Tarek Samy

Ebrahim Gomaa

## License This software is licensed under MIT License, See [MIT licensed](https://github.com/EmanOthman21/MIPS-Pipelined-Processor/blob/master/LICENSE)

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