CYUSB3KIT-003_with_SP605_xilinx
所属分类：VHDL/FPGA/Verilog
开发工具：C
文件大小：108467KB
下载次数：1
上传日期：2021-08-20 15:27:38
上 传 者：
sh-1993
说明： 该项目的目的是使用Cypress CYUSB3KIT-003 EZ-USB FX3 SuperSpeed Explorer Kit来编程和通信...
(This project aim is to use the Cypress CYUSB3KIT-003 EZ-USB FX3 SuperSpeed Explorer Kit to both program and communicate with a Xilinx Spartan 6 FPGA embedded on the SP605 Evaluation Kit. In order to connect both boards, the CYUSB3ACC-005 FMC Interconnect Board was used.)
文件列表:
Implementation_details.md (18420, 2021-08-20)
WireShark_Saves (0, 2021-08-20)
WireShark_Saves\Linux (0, 2021-08-20)
WireShark_Saves\Linux\complete_program.pcapng (231660, 2021-08-20)
WireShark_Saves\Linux\fpga_programming.pcapng (63032, 2021-08-20)
WireShark_Saves\Windows (0, 2021-08-20)
WireShark_Saves\Windows\fpga_firmware_only.pcapng (66292, 2021-08-20)
WireShark_Saves\Windows\full_programming_process.pcapng (1011608, 2021-08-20)
bin (0, 2021-08-20)
bin\FPGA Configuration Utility (0, 2021-08-20)
bin\FPGA Configuration Utility\CyUSB.dll (139264, 2021-08-20)
bin\FPGA Configuration Utility\Template.exe (17920, 2021-08-20)
bin\FPGA Configuration Utility\Template.pdb (28160, 2021-08-20)
bin\FPGA Configuration Utility\Template.vshost.exe (14328, 2021-08-20)
bin\FPGA Configuration Utility\Template.vshost.exe.manifest (479, 2021-08-20)
bin\FX3 firmware (0, 2021-08-20)
bin\FX3 firmware\ConfigFpgaSlaveFifoSync.img (142508, 2021-08-20)
bin\FX3 firmware\ConfigFpgaSlaveFifoSync_16.img (142284, 2021-08-20)
bin\FX3 firmware\ConfigFpgaSlaveFifoSync_32.img (142156, 2021-08-20)
bin\TEST.txt (1024, 2021-08-20)
bin\slaveFIFO2b_fpga_top.bin (1484684, 2021-08-20)
com_fpga (0, 2021-08-20)
com_fpga\FPGA_firmware (0, 2021-08-20)
com_fpga\FPGA_firmware\slaveFIFO2b_fpga_top.bin (1484684, 2021-08-20)
com_fpga\FPGA_firmware\slaveFIFO2b_fpga_top.bit (1484791, 2021-08-20)
com_fpga\TEST.txt (1024, 2021-08-20)
com_fpga\fpga_source_code (0, 2021-08-20)
com_fpga\fpga_source_code\fpga_slavefifo2b_verilog (0, 2021-08-20)
com_fpga\fpga_source_code\fpga_slavefifo2b_verilog\.Xil (0, 2021-08-20)
com_fpga\fpga_source_code\fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ (0, 2021-08-20)
com_fpga\fpga_source_code\fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ\ngc2edif (0, 2021-08-20)
com_fpga\fpga_source_code\fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ\ngc2edif\_xmsgs (0, 2021-08-20)
com_fpga\fpga_source_code\fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ\ngc2edif\_xmsgs\ngc2edif.xmsgs (523, 2021-08-20)
com_fpga\fpga_source_code\fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ\ngc2edif\ngc2edif.log (441, 2021-08-20)
com_fpga\fpga_source_code\fpga_slavefifo2b_verilog\.Xil\PlanAhead-23372-LAPWIN7-KEAJ\ngc2edif\slaveFIFO2b_fpga_top.edif (763237, 2021-08-20)
com_fpga\fpga_source_code\fpga_slavefifo2b_verilog\_ngo (0, 2021-08-20)
com_fpga\fpga_source_code\fpga_slavefifo2b_verilog\_ngo\netlist.lst (126, 2021-08-20)
... ...
# CYUSB3KIT-003 with SP605 xilinx
This project aim was to use the Cypress [CYUSB3KIT-003 EZ-USB FX3 SuperSpeed Explorer Kit](http://www.cypress.com/documentation/development-kitsboards/cyusb3kit-003-ez-usb-fx3-superspeed-explorer-kit)
to both **program** (upload the firmware of the FPGA using the kit) and **communicate** (make the FPGA send info and receive it with the PC and vice versa) with a Xilinx Spartan 6 FPGA embedded on the [SP605 Evaluation Kit](https://www.xilinx.com/products/boards-and-kits/ek-s6-sp605-g.html).
The implementation had to be adapted to a C++ code in linux so every CPU tool was then simulated on an own C++ code.
In order to connect both boards, the [CYUSB3ACC-005 FMC Interconnect Board](http://www.cypress.com/documentation/development-kitsboards/cyusb3acc-005-fmc-interconnect-board-ez-usb-fx3-superspeed) was used.
**Note:**
For confidentiality issues the integration of the whole project could not be uploaded but I uploaded what may be useful for other people that does not conflict with confidential agreement. The FPGA code was also merged into an existing code but I couldn't upload anything of it.
## Valuable content of the project
1. This project displays in a very detailed way how to connect the CYUSB3KIT with SP605 board.
2. Provides a class that enables a easy to use interface with Cypress devices for other implementations.
## Project Structure
- **docs**: Project's documentation like API functions.
- **fx3_manager_cpp_source**: Cpp project to communicate with FX3 device.
- **com_fpga**: firmware for both FPGA and FX3 to be able to perform a loopback communication between CPU and FPGA via FX3.
- **program_fpga**: Software needed to program the FPGA.
- **doc**: useful documentation from Cypress and Xilinx
## cpp Class for communicating with FX3
Inside [fx3_manager_cpp_source](https://github.com/NEGU93/CYUSB3KIT-003_with_SP605_xilinx/tree/master/fx3_manager_cpp_source) there's a cpp project that enables communication with the PC with the FX3. It gives and API that can be used for others to use a Cypress device in general.
Documentation: [Read the Docs](https://cyusb3kit-003-with-sp605-xilinx.readthedocs.io/en/latest/index.html)
When running the code (main function) it:
1. Programs the FX3 devices.
2. Programs the FPGA
3. Tries some loopback communication asserting the data sent is the same that the data received.
The communication to the FX3 device is done through a Cpp class that manages all the FX3 connection using cyusb library, who uses libusb-1.0. If the user want's to do it's own function he can just change the main.cpp and use the class created.
## Citations
I would like to know if this explanations or code was useful to somebody so if it's the case let me know (star the project for ex.)
Just use this as you need!
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