jishi
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:3KB
下载次数:4
上传日期:2011-08-29 10:44:09
上 传 者:
zhangfengwei3
说明: 带有寄存器的实时钟,能设定时间,然后时钟跑动。
(With the register of real-time clock, can set the time, then the clock running.)
文件列表:
top.v (1112, 2011-08-25)
clock2.v (1384, 2011-08-27)
clock.v (5167, 2011-08-25)
regester.v (2094, 2011-08-27)
runnian.v (758, 2011-08-23)
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