文件列表:

Xilinx_2 (0, 2006-03-31)
Xilinx_2\Example-4-1 (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\Mix (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\Mix\xilinx_lib (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\Mix\xilinx_lib\gen_4k (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\Mix\xilinx_lib\gen_virtex (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\Mix\xilinx_lib\gen_virtex2 (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\rev_1 (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\rev_1\syntmp (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\rev_2 (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\rev_2\syntmp (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\verilog (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\vhdl (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\源代码 (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\源代码\verilog (0, 2006-03-31)
Xilinx_2\Example-4-1\Synplify_Pro\源代码\VHDL (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例 (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703 (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\bufgce_instanciate (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\bufgmux_instanciate (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\dcm (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\dcm_instanciate (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\dcm_instanciate\frequency_synthesis (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\dcm_instanciate\phase_shifting (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ddr (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ddr\input (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ddr_instanciate (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ddr_instanciate\bi_dir_instanciate (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ddr_instanciate\output_instanciate (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\mult18x18 (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\mult18x18s (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\mult18x18s_instanciate (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\mult_and (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ram (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ram\default (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ram\default\synthesis (0, 2006-03-31)
Xilinx_2\Example-4-1\Xilinx示例\hdl_example_v2_synplify\spro_703\verilog\ram\default\synthesis\syntmp (0, 2006-03-31)
... ...

Readme.txt for AM2910 sample design package: lib.vhd - analyze into library LIB source files: am2910.vhd bts4.vhd control.vhd regcnt.vhd stack.vhd upc.vhd y.vhd Root: am2910.vhd/am2910 External reference: gtech TBUF Notes: The original design uses component BTS4. I created a file bts4 and implemented BTS4 using TBUF. Hence, this design can be targetted at any architecture supporting TBUF

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