Task01_Led
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:903KB
下载次数:6
上传日期:2011-09-01 14:55:31
上 传 者:
1988saladin
说明: 基于Spartan 3E的FPGA的流水LEd灯演示工程
(Base on Spartan-3E-FPGA flow led Project)
文件列表:
Task01_Led\.lso (6, 2011-07-01)
Task01_Led\current_webtalk_impact.xml (1413, 2011-07-01)
Task01_Led\default_waveform.pdf (5040, 2011-07-04)
Task01_Led\fuse.log (1161, 2011-07-01)
Task01_Led\fuse.xmsgs (367, 2011-07-01)
Task01_Led\fuseRelaunch.cmd (235, 2011-07-01)
Task01_Led\impact.xsl (1477, 2011-08-30)
Task01_Led\impact_impact.xwbt (195, 2011-08-30)
Task01_Led\in_out.ucf (836, 2011-07-01)
Task01_Led\iseconfig\Led.xreport (20665, 2011-08-30)
Task01_Led\iseconfig\Task01_Led.projectmgr (9254, 2011-07-14)
Task01_Led\isim\isim_usage_statistics.html (1664, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\isimcrash.log (0, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\ISimEngine-DesignHierarchy.dbg (4146, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\isimkernel.log (564, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\Led_testbench_isim_beh.exe (31425, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\netId.dat (36, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\tmp_save\_1 (2095, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\Led_testbench_isim_beh.exe_main.c (1353, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\Led_testbench_isim_beh.exe_main.nt.obj (1274, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\m_00000000001423698400_2692072982.c (4180, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\m_00000000001423698400_2692072982.didat (2816, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\m_00000000001423698400_2692072982.nt.obj (1986, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\m_00000000003296313554_0697561182.c (22712, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\m_00000000003296313554_0697561182.didat (3056, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\m_00000000003296313554_0697561182.nt.obj (13392, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\m_00000000004093713498_2073120511.c (7967, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\m_00000000004093713498_2073120511.didat (5412, 2011-07-01)
Task01_Led\isim\Led_testbench_isim_beh.exe.sim\work\m_00000000004093713498_2073120511.nt.obj (3134, 2011-07-01)
Task01_Led\isim\pn_info (6, 2011-07-01)
Task01_Led\isim\temp\@led.sdb (10595, 2011-07-01)
Task01_Led\isim\temp\@led_testbench.sdb (1510, 2011-07-01)
Task01_Led\isim\temp\glbl.sdb (4474, 2011-07-01)
Task01_Led\isim\work\@led.sdb (10585, 2011-07-01)
Task01_Led\isim\work\@led_testbench.sdb (1500, 2011-07-01)
Task01_Led\isim\work\glbl.sdb (4464, 2011-07-01)
Task01_Led\isim.cmd (44, 2011-07-01)
Task01_Led\isim.log (403, 2011-07-01)
Task01_Led\led.bgn (8771, 2011-07-04)
Task01_Led\led.bit (341687, 2011-07-04)
... ...
The following files were generated for 'icon_pro' in directory
D:\ISE_Work\Task01_Led\_ngo\cs_icon_pro\
icon_pro.ejp:
Please see the core data sheet.
icon_pro.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
icon_pro.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
icon_pro.vhd:
Unisim VHDL file containing the information required to simulate
the module.
icon_pro.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
icon_pro.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
icon_pro.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
icon_pro_readme.txt:
Text file indicating the files generated and how they are used.
icon_pro_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
icon_pro_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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