FPGA_OTDR_Project
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：869KB
下载次数：1
上传日期：2021-11-17 05:31:44
上 传 者：
sh-1993
说明： 用于光纤网络分析的OTDR的FPGA实现。使用的内存是ZBT Ram（零总线翻转）
(FPGA Implementation of OTDR for analysis of fiber optic network . The memory used is ZBT Ram ( Zero Bus Turnaround))
文件列表:
AE_top_lib.vhd (16557, 2021-11-17)
AEregisters.vhd (8011, 2021-11-17)
AEtop.vhd (24881, 2021-11-17)
AExlatAR.vhd (2652, 2021-11-17)
AExlatRR.vhd (1839, 2021-11-17)
DSP_emifs.vhd (1035, 2021-11-17)
FPGA based OTDR Measurement.pdf (927450, 2021-11-17)
LAN91C96.vhd (1938, 2021-11-17)
PLL.vhd (18186, 2021-11-17)
clkctrl.vhd (6032, 2021-11-17)
fsm_pll.vhd (16798, 2021-11-17)
package_utility.vhd (2089, 2021-11-17)
pulse_delay.vhd (9240, 2021-11-17)
pulse_gen.vhd (1741, 2021-11-17)
pulse_top.vhd (3958, 2021-11-17)
source (0, 2021-11-17)
source\AE_top_lib.vhd (16086, 2021-11-17)
source\AEregisters.vhd (7822, 2021-11-17)
source\AEtop.vhd (24881, 2021-11-17)
source\AExlatAR.vhd (2583, 2021-11-17)
source\AExlatRR.vhd (1783, 2021-11-17)
source\DSP_emifs.vhd (1005, 2021-11-17)
source\LAN91C96.vhd (1881, 2021-11-17)
source\PLL.vhd (17768, 2021-11-17)
source\clkctrl.vhd (5852, 2021-11-17)
source\fsm_pll.vhd (16411, 2021-11-17)
source\package_utility.vhd (2016, 2021-11-17)
source\pulse_delay.vhd (8975, 2021-11-17)
source\pulse_gen.vhd (1679, 2021-11-17)
source\pulse_top.vhd (3814, 2021-11-17)
source\tb_aetop.vhd (20470, 2021-11-17)
tb_aetop.vhd (21101, 2021-11-17)
# FPGA_OTDR_Project
The algorithm for OTDR measurement is implemented on a Alteras Cyclone FPGA .This embedded FSM machine generates a logic pulse of varying width from 10ns to 10us to analyze fiber optic cable from 10 meters to 10 Km. This pulse will turn the laser LED on for the set duration. The user can also set delay of this pulse in steps of +/-1.25us. The set delay of Laser firing pulse is in reference to start of data acquisition from ADC (Analog to Digital Converter). After the master unit which can be a microprocessor sets the pulse width and pulse delay step the Acquisition State Machine (OTDR Core) will turn the Laser LED on for the set parameter. The laser pulse travelling into the fiber-optic cable will generate back-scatter radiation (Rayleigh scattering). The intensity of back-scatter light from the travelling-pulse will vary as it encounters joints and splices throughout the length of fiber-cable. ADC will sample voltage generated from high performance photo-diode installed at the same end of fiber-cable as the Laser diode. Figure 3 shows block diagram of FPGA based OTDR hardware implementation. The optical MUX/DEMUX will select optical input when transmitting laser pulse and optical output when doing OTDR measurements. Data acquired over a million iterations will be saved and re-written on to a ZBT RAM which can be retrieved by a master controller.
Author : Ahmed Asim Ghouri
Email : asimghr@gmail.com
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