Four-Responder

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:9KB
下载次数:6
上传日期:2011-09-07 16:02:06
上 传 者jingqinshan
说明:  (1)设计用于竞赛抢答的四人抢答器; .有多路抢答,抢答台数为4; .具有抢答开始后20秒倒计时,20秒倒计时后无人抢答显示超时,并报警; .能显示超前抢答台号并显示犯规警报; (2) 系统复位后进入抢答状态,当有一路抢答按键按下,该路抢答信号将其余各路抢答信号封锁,同时铃声想起,直至该路按键松开,显示牌显示该路抢答台号;
((1) is designed to answer in the four competition Responder . More way to answer in the number of answer in units of 4 . With the answer in 20 seconds after starting the countdown, 20 seconds after the countdown show no answer in overtime, and alarm . Can Display answer in advance and display the foul alarm station number (2) to enter the answer in the state after a system reset, when a button is pressed all the way to answer in the answer in the signal to the rest of the brightest way to answer in the signal block, and ring tones recall, release the button until the road , road signs show the answer in station ID )

文件列表:
Four Responder.doc (72192, 2011-09-07)

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