文件列表:

interrupts (0, 2011-06-24)
interrupts\interrupts.c (14477, 2007-09-03)
interrupts\interrupts.Opt (1727, 2007-09-03)
interrupts\interrupts.Uv2 (2885, 2007-09-03)
interrupts\lst (0, 2011-06-24)
interrupts\lst\interrupts.map (35142, 2007-09-03)
interrupts\obj (0, 2011-06-24)
interrupts\obj\interrupts.axf (36424, 2007-09-03)
interrupts\obj\interrupts.bin (4056, 2007-09-03)
interrupts\Startup.s (10657, 2007-09-03)

Interrupts This example application demonstrates the interrupt preemption and tail-chaining capabilities of Cortex-M3 microprocessor and NVIC. Nested interrupts are synthesized when the interrupts have the same priority, increasing priorities, and decreasing priorities. With increasing priorities, preemption will occur; in the other two cases tail-chaining will occur. The currently pending interrupts and the currently executing interrupt will be displayed on the OLED; GPIO pins B0, B1 and B2 will be asserted upon interrupt handler entry and de-asserted before interrupt handler exit so that the off-to-on time can be observed with a scope or logic analyzer to see the speed of tail-chaining (for the two cases where tail-chaining is occurring). ------------------------------------------------------------------------------- Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. Software License Agreement Luminary Micro, Inc. (LMI) is supplying this software for use solely and exclusively on LMI's microcontroller products. The software is owned by LMI and/or its suppliers, and is protected under applicable copyright laws. All rights are reserved. Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil liability for the breach of the terms and conditions of this license. THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. This is part of revision 1582 of the Stellaris Peripheral Driver Library.

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