文件列表:

ethmac\.svn\all-wcprops (182, 2011-02-03)
ethmac\.svn\dir-prop-base (28, 2011-02-03)
ethmac\.svn\entries (384, 2011-02-03)
ethmac\bench\.svn\all-wcprops (86, 2011-02-03)
ethmac\bench\.svn\entries (207, 2011-02-03)
ethmac\bench\verilog\.svn\all-wcprops (1848, 2011-02-03)
ethmac\bench\verilog\.svn\entries (2340, 2011-02-03)
ethmac\bench\verilog\.svn\text-base\eth_host.v.svn-base (4621, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\eth_memory.v.svn-base (5836, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\eth_phy.v.svn-base (41421, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\eth_phy_defines.v.svn-base (4393, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\tb_cop.v.svn-base (13483, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\tb_ethernet.v.svn-base (975590, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\tb_ethernet_with_cop.v.svn-base (19643, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\tb_eth_defines.v.svn-base (10574, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\tb_eth_top.v.svn-base (51437, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\wb_bus_mon.v.svn-base (18743, 2011-02-03)
ethmac\bench\verilog\.svn\text-base\wb_master32.v.svn-base (13486, 2011-02-03)
ethmac\bench\verilog\.svn\text-base\wb_master_behavioral.v.svn-base (23268, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\wb_model_defines.v.svn-base (7223, 2011-02-02)
ethmac\bench\verilog\.svn\text-base\wb_slave_behavioral.v.svn-base (12219, 2011-02-02)
ethmac\bench\verilog\eth_host.v (4621, 2011-02-02)
ethmac\bench\verilog\eth_memory.v (5836, 2011-02-02)
ethmac\bench\verilog\eth_phy.v (41421, 2011-02-02)
ethmac\bench\verilog\eth_phy_defines.v (4393, 2011-02-02)
ethmac\bench\verilog\tb_cop.v (13483, 2011-02-02)
ethmac\bench\verilog\tb_ethernet.v (975590, 2011-02-02)
ethmac\bench\verilog\tb_ethernet_with_cop.v (19643, 2011-02-02)
ethmac\bench\verilog\tb_eth_defines.v (10574, 2011-02-02)
ethmac\bench\verilog\tb_eth_top.v (51437, 2011-02-02)
ethmac\bench\verilog\wb_bus_mon.v (18743, 2011-02-03)
ethmac\bench\verilog\wb_master32.v (13486, 2011-02-03)
ethmac\bench\verilog\wb_master_behavioral.v (23268, 2011-02-02)
ethmac\bench\verilog\wb_model_defines.v (7223, 2011-02-02)
ethmac\bench\verilog\wb_slave_behavioral.v (12219, 2011-02-02)
ethmac\doc\.svn\all-wcprops (628, 2011-02-03)
ethmac\doc\.svn\entries (891, 2011-02-03)
ethmac\doc\.svn\prop-base\ethernet_datasheet_OC_head.pdf.svn-base (53, 2011-02-03)
ethmac\doc\.svn\prop-base\ethernet_product_brief_OC_head.pdf.svn-base (53, 2011-02-03)
... ...

////////////////////////////////////////////////////////////////////// //// //// //// README.txt //// //// //// //// This file is part of the Ethernet IP core project //// //// http://www.opencores.org/projects/ethmac/ //// //// //// //// Author(s): //// //// - Igor Mohor (igorM@opencores.org) //// //// //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001, 2002 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // // // RUNNING the simulation/Testbench in ModelSIM: Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf Run the macro do.do (write "do do.do" in the command window). Simulation will be automatically started. Logs are stored in the /log directory. tb_ethernet test is performed. RUNNING the simulation/Testbench in Ncsim: Go to the ethernet\sim\rtl_sim\ncsim_sim\run directory. Run the run_eth_sim_regr.scr script. Simulation is automatically started. Logs are stored in the /log directory. Before running the script for another time, run the clean script that deletes files from previous runs. tb_ethernet test is performed. Why are eth_cop.v, eth_host.v, eth_memory, tb_cop.v and tb_ethernet_with_cop.v files used for? Although the testbench does not include the traffic coprocessor, the coprocessor is part of the ethernet environment. eth_cop multiplexes two wishbone interface between 4 modules: - First wishbone master interface is connected to the HOST (eth_host) - Second wishbone master interface is connected to the Ethernet Core (for accessing data in the memory (eth_memory)). - First wishbone slave interface is connected to the Ethernet Core (for accessing registers and buffer descriptors). - Second wishbone slave interface is connected to the memory (eth_memory) so host can write data to the memory (or read data from the memory. tb_cop.c is a testbench just for the traffic coprocessor (eth_cop). tb_ethernet_with_cop.v is a simple testbench where all above mentioned modules are connected into a single environment. Few packets are transmitted and received. The "main" testbench is tb_ethernet.v file. It performs several tests (eth_cop is not part of the simulation environment).

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