i2c-verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：215KB
下载次数：5
上传日期：2011-09-16 16:19:14
上 传 者：
easygirlss
说明： 可进行i2c读写操作I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of
data exchange between devices. It is most suitable
(it can write and read codes in i2c.I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of
data exchange between devices. It is most suitable)
文件列表:
rtl\CVS\Root (62, 2008-03-30)
rtl\CVS\Repository (9, 2008-03-30)
rtl\CVS\Template (0, 2008-07-27)
rtl\CVS\Entries (27, 2008-03-30)
rtl\CVS\Entries.Extra (33, 2008-03-30)
rtl\verilog\CVS\Root (62, 2008-03-30)
rtl\verilog\CVS\Repository (17, 2008-03-30)
rtl\verilog\CVS\Template (0, 2008-07-27)
rtl\verilog\CVS\Entries (265, 2008-03-30)
rtl\verilog\CVS\Entries.Extra (145, 2008-03-30)
rtl\verilog\i2c_master_bit_ctrl.v (18025, 2006-09-04)
rtl\verilog\i2c_master_byte_ctrl.v (10891, 2004-02-18)
rtl\verilog\i2c_master_defines.v (3283, 2001-11-05)
rtl\verilog\i2c_master_top.v (10409, 2005-02-27)
rtl\verilog\timescale.v (25, 2001-09-24)
rtl\vhdl\CVS\Root (62, 2008-03-30)
rtl\vhdl\CVS\Repository (14, 2008-03-30)
rtl\vhdl\CVS\Template (0, 2008-07-27)
rtl\vhdl\CVS\Entries (300, 2008-03-30)
rtl\vhdl\CVS\Entries.Extra (158, 2008-03-30)
rtl\vhdl\I2C.VHD (14162, 2001-09-24)
rtl\vhdl\i2c_master_bit_ctrl.vhd (18768, 2006-10-11)
rtl\vhdl\i2c_master_byte_ctrl.vhd (13218, 2004-02-18)
rtl\vhdl\i2c_master_top.vhd (13803, 2004-03-14)
rtl\vhdl\tst_ds1621.vhd (7242, 2001-09-24)
rtl\verilog\CVS (0, 2008-03-30)
rtl\vhdl\CVS (0, 2008-03-30)
rtl\CVS (0, 2008-03-30)
rtl\verilog (0, 2008-03-30)
rtl\vhdl (0, 2008-03-30)
rtl (0, 2008-03-30)
i2c-verilog.pdf (211471, 2011-05-06)
-- This code is provided for free and may be used and --
-- distributed without restriction provided that the --
-- copyright statement is not removed from the file and --
-- that any derivative work contains the original --
-- copyright notice and the associated disclaimer. --
-- Comments and suggestions are always welcome --
The i2c_master core consists of three files:
- i2c_master_top -- top level
- i2c_master_byte_ctrl -- byte controller
- i2c_master_bit_ctrl -- bit controller
VHDL needs to be compiled in order. The files are listed
above in descending order.
I2C.VHD and tst_ds1621.vhd are not supported anymore.
They remain mostly for historical purposes, altough they
might prove usefull.
Richard Herveille
rherveille@opencores.org
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