SAP1pond
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：577KB
下载次数：5
上传日期：2011-09-19 21:23:41
上 传 者：
casentia
说明： SAP1 Using VHDL instead of presenting in Proteus
文件列表:
SAP1\.lso (6, 2011-09-18)
SAP1\ALU.prj (21, 2011-09-17)
SAP1\ALU.stx (737, 2011-09-17)
SAP1\ALU.vhd (1639, 2011-09-17)
SAP1\ALU.xst (71, 2011-09-17)
SAP1\BCD_decoder.prj (29, 2011-09-17)
SAP1\BCD_decoder.spl (64, 2011-09-17)
SAP1\BCD_decoder.stx (753, 2011-09-17)
SAP1\BCD_decoder.sym (589, 2011-09-17)
SAP1\BCD_decoder.vhd (1472, 2011-09-17)
SAP1\BCD_decoder.xst (79, 2011-09-17)
SAP1\CM.cmd_log (375, 2011-09-18)
SAP1\CM.lso (6, 2011-09-18)
SAP1\CM.prj (20, 2011-09-18)
SAP1\CM.syr (4462, 2011-09-18)
SAP1\CM.vhd (3627, 2011-09-18)
SAP1\CM.xst (1036, 2011-09-18)
SAP1\CM_summary.html (2764, 2011-09-18)
SAP1\CU.cmd_log (150, 2011-09-18)
SAP1\CU.lso (6, 2011-09-18)
SAP1\CU.ngc (34685, 2011-09-18)
SAP1\CU.ngr (24816, 2011-09-18)
SAP1\CU.prj (110, 2011-09-18)
SAP1\CU.stx (1231, 2011-09-18)
SAP1\CU.syr (33356, 2011-09-18)
SAP1\CU.vhd (3643, 2011-09-18)
SAP1\CU.xst (1036, 2011-09-18)
SAP1\CU_summary.html (3830, 2011-09-18)
SAP1\gen_CLK250Hz.prj (50, 2011-09-18)
SAP1\gen_CLK250Hz.stx (957, 2011-09-18)
SAP1\gen_CLK250Hz.vhd (1506, 2010-10-05)
SAP1\gen_CLK250Hz.xst (80, 2011-09-18)
SAP1\gen_CLK250Hz_vhdl.prj (72, 2011-09-18)
SAP1\ID.prj (20, 2011-09-18)
SAP1\ID.stx (755, 2011-09-18)
SAP1\ID.vhd (1371, 2011-09-18)
SAP1\ID.xst (70, 2011-09-18)
SAP1\IR.vhd (1272, 2011-09-18)
SAP1\JK-FF.vhd (1240, 2011-09-18)
SAP1\JKFF.cmd_log (79, 2011-09-18)
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