CSE460_Labs
所属分类：VHDL/FPGA/Verilog
开发工具：HTML
文件大小：16376KB
下载次数：3
上传日期：2022-04-18 17:13:57
上 传 者：
sh-1993
说明： 这个回购包含我在BracU的CSE460:VLSI课程的实验室文件，用VHDL、DHCP和MicroWind编写。
(This repo contains the lab files for my CSE460: VLSI course at BracU, written in VHDL, DHCP and MicroWind.)
文件列表:
.DS_Store (6148, 2022-04-19)
Assessments (0, 2022-04-19)
Assessments\Lab 2 Assessment (0, 2022-04-19)
Assessments\Lab 2 Assessment\Compilation.png (127135, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.asm.rpt (9119, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.done (26, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.eda.rpt (7861, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.fit.rpt (28125, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.fit.summary (394, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.flow.rpt (7905, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.map.rpt (15003, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.map.summary (308, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.pin (18535, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.qpf (920, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.qsf (2486, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.qws (540, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.sim.rpt (11069, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.sof (57969, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.tan.summary (1438, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.v (266, 2022-04-19)
Assessments\Lab 2 Assessment\Lab_2_Assessment.vwf (5586, 2022-04-19)
Assessments\Lab 2 Assessment\db (0, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.(0).cnf.cdb (1014, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.(0).cnf.hdb (539, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.asm.qmsg (2026, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.cbx.xml (98, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.cmp.hdb (6926, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.cmp.logdb (4, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.cmp.rdb (10923, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.cmp.tdb (2155, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.cmp0.ddb (2897, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.db_info (136, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.eda.qmsg (2909, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.eds_overflow (2, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.fit.qmsg (5033, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.fnsim.cdb (1030, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.fnsim.hdb (7007, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.hier_info (471, 2022-04-19)
Assessments\Lab 2 Assessment\db\Lab_2_Assessment.hif (829, 2022-04-19)
... ...
# CSE460_Labs
This repo contains the lab files for my CSE460: VLSI course at BracU, written in VHDL, DSCH and MicroWind.
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