5 Stages Pipeline ARM CPU System Verilog Implemen
所属分类：源码/资料
开发工具：Verilog
文件大小：31KB
下载次数：0
上传日期：2022-05-14 21:38:00
上 传 者：
jiyongbo
说明： 5线程VERILOG语言编写的CPU系统。
文件列表:
2To4Decoder.sv (627, 2020-09-25)
ALU.sv (706, 2020-09-25)
Branches.sv (1299, 2020-09-25)
CPU.sv (1921, 2020-09-25)
CPU_control.sv (3748, 2020-09-25)
CPU_datapath.sv (2019, 2020-09-25)
DE1_SoC.sv (31, 2020-09-25)
DFF64bit.sv (264, 2020-09-25)
DFFEn.sv (1473, 2020-09-25)
D_FF.sv (540, 2020-09-25)
ExtendedConstant.sv (1163, 2020-09-25)
FiveBit_Reg.sv (325, 2020-09-25)
FiveTo32Decoder.sv (783, 2020-09-25)
FourToOneMux.sv (649, 2020-09-25)
FourToSixteenDecoder.sv (1360, 2020-09-25)
MemCircuit.sv (508, 2020-09-25)
PC.sv (177, 2020-09-25)
PCInstruction.sv (432, 2020-09-25)
PCcircuit.sv (1172, 2020-09-25)
RegCircuit.sv (657, 2020-09-25)
RegData.sv (29, 2020-09-25)
SixBit_Reg.sv (324, 2020-09-25)
SixteenToOneMux.sv (609, 2020-09-25)
SixtyFourBitThirtyTwoToOneMux.sv (1113, 2020-09-25)
SixtyFour_Bit_Register.sv (1378, 2020-09-25)
ThirtyTwoToOneMux.sv (728, 2020-09-25)
ThirtyTwo_Bit_Register.sv (341, 2020-09-25)
ThreeBit_Reg.sv (326, 2020-09-25)
TwoToFourDecoder.sv (978, 2020-09-25)
TwoToOneMux.sv (671, 2020-09-25)
TwoToOneMux5bit.sv (572, 2020-09-25)
TwoToOneMux64bit.sv (627, 2020-09-25)
adderMux.sv (1109, 2020-09-25)
alustim.sv (5116, 2020-09-25)
and16.sv (549, 2020-09-25)
bitALU.sv (2446, 2020-09-25)
datamem.sv (3932, 2020-09-25)
eightToOneMux.sv (600, 2020-09-25)
ex_reg.sv (2743, 2020-09-25)
... ...
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