uart2bus
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：39KB
下载次数：15
上传日期：2011-10-05 00:58:25
上 传 者：
csuusc
说明： uart接口到内部总线的IP核，采用VDHL和VERILOG语言编写。
(UART interface to Bus IP Core in VHDL and verilog languages)
文件列表:
scilab\calc_baud_gen.sce (1682, 2011-03-25)
verilog\sim\icarus\gtk.bat (30, 2010-02-15)
verilog\sim\icarus\compile_bin.bat (38, 2010-04-03)
verilog\sim\icarus\block_bin.cfg (223, 2010-04-03)
verilog\sim\icarus\block_txt.cfg (223, 2010-04-03)
verilog\sim\icarus\test.bin (28, 2010-02-15)
verilog\sim\icarus\compile_txt.bat (38, 2010-04-03)
verilog\sim\icarus\run.bat (27, 2010-02-15)
verilog\sim\icarus\test.txt (46, 2010-02-15)
verilog\bench\timescale.v (242, 2010-02-15)
verilog\bench\tb_uart2bus_top.v (5421, 2010-02-15)
verilog\bench\tb_txt_uart2bus_top.v (5429, 2010-04-03)
verilog\bench\uart_tasks.v (7726, 2010-02-15)
verilog\bench\reg_file_model.v (2100, 2010-02-15)
verilog\bench\tb_bin_uart2bus_top.v (6563, 2010-04-03)
verilog\syn\altera\uart2bus_top.qsf (3281, 2010-02-15)
verilog\syn\altera\uart2bus.qpf (1288, 2010-02-15)
verilog\syn\altera\uart2bus.qws (90, 2010-02-15)
verilog\syn\xilinx\uart2bus.xise (3601, 2010-02-15)
verilog\rtl\uart2bus_top.v (2990, 2010-04-03)
verilog\rtl\uart_rx.v (3213, 2010-02-15)
verilog\rtl\uart_top.v (2229, 2010-02-15)
verilog\rtl\uart_tx.v (2618, 2010-02-15)
verilog\rtl\uart_parser.v (19888, 2010-02-15)
verilog\rtl\baud_gen.v (1851, 2010-02-15)
vhdl\test.bin (28, 2010-07-18)
vhdl\bench\uart2BusTop_bin_tb.vhd (8200, 2010-07-18)
vhdl\bench\uart2BusTop_txt_tb.vhd (6440, 2010-07-18)
vhdl\bench\regFileModel.vhd (1903, 2010-07-18)
vhdl\syn\xilinx\uart2bus.xise (36945, 2010-07-18)
vhdl\rtl\uart2BusTop.vhd (4177, 2010-07-18)
vhdl\rtl\uartTop.vhd (3195, 2010-07-18)
vhdl\rtl\uartParser.vhd (26012, 2010-07-18)
vhdl\rtl\uartTx.vhd (3316, 2010-07-18)
vhdl\rtl\uartRx.vhd (3994, 2010-07-18)
vhdl\rtl\baudGen.vhd (1898, 2010-07-18)
vhdl\test.txt (46, 2010-07-18)
verilog\sim\icarus (0, 2011-10-05)
verilog\syn\altera (0, 2011-10-05)
verilog\syn\xilinx (0, 2011-10-05)
... ...
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