open-register-design-tool
所属分类：大数据
开发工具：Verilog
文件大小：2515KB
下载次数：0
上传日期：2022-09-04 04:26:27
上 传 者：
sh-1993
说明： 开放寄存器设计工具，使用SystemRDL或JSpec输入生成寄存器RTL、模型和文档的工具
(open-register-design-tool,Tool to generate register RTL, models, and docs using SystemRDL or JSpec input)
文件列表:
LICENSE (11341, 2019-10-21)
build.gradle (4405, 2019-10-21)
example.parms (9312, 2019-10-21)
gradle (0, 2019-10-21)
gradle\wrapper (0, 2019-10-21)
gradle\wrapper\gradle-wrapper.jar (54727, 2019-10-21)
gradle\wrapper\gradle-wrapper.properties (200, 2019-10-21)
gradlew (5296, 2019-10-21)
gradlew.bat (2176, 2019-10-21)
settings.gradle (155, 2019-10-21)
src (0, 2019-10-21)
src\ordt (0, 2019-10-21)
src\ordt\annotate (0, 2019-10-21)
src\ordt\annotate\AnnotateCommand.java (6687, 2019-10-21)
src\ordt\annotate\AnnotateNullCommand.java (510, 2019-10-21)
src\ordt\annotate\AnnotateSetCommand.java (2801, 2019-10-21)
src\ordt\annotate\AnnotateShowCommand.java (1815, 2019-10-21)
src\ordt\extract (0, 2019-10-21)
src\ordt\extract\DebugController.java (741, 2019-10-21)
src\ordt\extract\DefinedProperties.java (19708, 2019-10-21)
src\ordt\extract\DefinedProperty.java (7576, 2019-10-21)
src\ordt\extract\JSpecModelExtractor.java (63120, 2019-10-21)
src\ordt\extract\MyDebugController.example (4424, 2019-10-21)
src\ordt\extract\Ordt.java (19451, 2019-10-21)
src\ordt\extract\OverlayFileInfo.java (322, 2019-10-21)
src\ordt\extract\PropertyList.java (10645, 2019-10-21)
src\ordt\extract\RdlModelExtractor.java (48057, 2019-10-21)
src\ordt\extract\RegModelIntf.java (787, 2019-10-21)
src\ordt\extract\RegNumber.java (24212, 2019-10-21)
src\ordt\extract\model (0, 2019-10-21)
src\ordt\extract\model\ModAddressableInstance.java (6083, 2019-10-21)
src\ordt\extract\model\ModBaseComponent.java (7771, 2019-10-21)
src\ordt\extract\model\ModComponent.java (26957, 2019-10-21)
src\ordt\extract\model\ModEnum.java (3437, 2019-10-21)
src\ordt\extract\model\ModEnumElement.java (2497, 2019-10-21)
src\ordt\extract\model\ModField.java (1965, 2019-10-21)
src\ordt\extract\model\ModFieldSet.java (4278, 2019-10-21)
... ...
# open-register-design-tool
Ordt is a tool for automation of IC register definition and documentation. It currently supports 2 input formats:
1. SystemRDL - a stardard register description format released by [Accellera.org](http://accellera.org/activities/working-groups/systemrdl)
2. JSpec - a register description format used within Juniper Networks
The tool can generate several outputs from SystemRDL or JSpec, including:
- SystemVerilog/Verilog RTL code description of registers
- UVM model of the registers
- C++ and python models of the registers
- XML and text file register descriptions
- SystemRDL and JSpec (conversion)
Easiest way to get started with ordt is to download a runnable jar from the [release area](https://github.com/Juniper/open-register-design-tool/releases).
Ordt documentation can be found [here](https://github.com/Juniper/open-register-design-tool/wiki).
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