5B6B-codec

所属分类:VHDL/FPGA/Verilog
开发工具:Others
文件大小:4KB
下载次数:60
上传日期:2011-10-08 22:41:21
上 传 者哦十全_学习ing
说明:  verilog hdl实现5B6B编译码(光纤通信线路码型),包含了时钟发生器模块 ,信号源模块 ,编码模块 ,译码模块, 和检错模块,并通过modesim仿真验证。
(verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, decoding module, and error detection module, and through modesim simulation.)

文件列表:
5B6B编译码\check_error.v (5190, 2011-05-15)
5B6B编译码\clk_generate.v (1287, 2011-04-24)
5B6B编译码\coder.v (6017, 2011-04-24)
5B6B编译码\encoder.v (3584, 2011-05-04)
5B6B编译码\fiveB_sixB_encoder.v (1301, 2011-05-07)
5B6B编译码\signal_source.v (943, 2011-04-24)
5B6B编译码\test.v (570, 2011-05-08)
5B6B编译码 (0, 2011-05-27)

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