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firmware (0, 2022-05-19)
firmware\FPGA (0, 2022-05-19)
firmware\FPGA\nvm_ctrl.ccl (17, 2022-05-19)
firmware\FPGA\nvm_ctrl.ldf (1033, 2022-05-19)
firmware\FPGA\nvm_ctrl.lpf (1640, 2022-05-19)
firmware\FPGA\nvm_ctrl.v (12154, 2022-05-19)
firmware\FPGA\nvm_ctrl (0, 2022-05-19)
firmware\FPGA\nvm_ctrl\.build_status (3236, 2022-05-19)
firmware\FPGA\nvm_ctrl\.vdbs (0, 2022-05-19)
firmware\FPGA\nvm_ctrl\.vdbs\dbStat.txt (26, 2022-05-19)
firmware\FPGA\nvm_ctrl\.vdbs\nvm_ctrl_nvm_ctrl_map.vdb (222282, 2022-05-19)
firmware\FPGA\nvm_ctrl\.vdbs\nvm_ctrl_nvm_ctrl_rtl.vdb (543266, 2022-05-19)
firmware\FPGA\nvm_ctrl\.vdbs\nvm_ctrl_nvm_ctrl_tech.vdb (282594, 2022-05-19)
firmware\FPGA\nvm_ctrl\automake.err (20445, 2022-05-19)
firmware\FPGA\nvm_ctrl\automake.log (44127, 2022-05-19)
firmware\FPGA\nvm_ctrl\hdla_gen_hierarchy.html (6505, 2022-05-19)
firmware\FPGA\nvm_ctrl\message.xml (18240, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl.xcf (1709, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_drc.log (857, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_lse.twr (21380, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_lse_lsetwr.html (23452, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.alt (1568, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.arearep (2250, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.bgn (4308, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.bit (12231, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.dir (0, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.dir\5_1.ncd (588951, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.dir\5_1.pad (21537, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.dir\5_1.par (8671, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.dir\5_1_par.asd (2218, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.dir\nvm_ctrl_nvm_ctrl.par (1182, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.drc (38, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.jed (348444, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.log (95, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.lpf (66, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.lsedata (1197277, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.mrp (19366, 2022-05-19)
firmware\FPGA\nvm_ctrl\nvm_ctrl_nvm_ctrl.ncd (588951, 2022-05-19)
... ...

## What is in this repository? Here is the complete set of design files, manufacturing data, source files, test results and other resources that I used in the process of building a nanovoltmeter. This process was not a coincidence, but a response to the nanovoltmeter challenge by TiN on [his website](https://xdevs.com/article/nvm_comp/)  ## What is a nanovoltmeter and what is it good for? Well, a nanovoltmeter is a voltmeter that has the sensitivity, noise and stability to resolve voltages down to the nanovolt. While many multimeters do have quite sensitive low voltage ranges, the resolution (least significant digit) is usually in the order of hundreds of nanovolts - and value of this last digit is often diminished by the noise and nonlinearity of the meter. So, for proper low signal measurements, having a higher sensitivity is mandatory. Measurement of such low voltages is useful for many applications, for example resolving small voltage differences in various differential and bridge circuits and the measurement of very small resistances - with an appropriate current source. Commercial nanovoltmeters do exist, like the Keithley model 2182A or Keysight 34420A, but with a hefty price tag, so a DIY design definitely has its place. ## xDevs challenge While I have been tinkering with DIY test and measurement tools for a while now, I never had an impulse to discover the nanovolt world. Such a trigger happened on September 2nd, 2021, when TiN from xdevs site launched the [nanovolt challenge](https://xdevs.com/article/nvm_comp/). In nutshell, it called for the design of an open-source nanovoltmeter, with parameters comparable to commercial designs and a timeframe of 256 days. That is a non-trivial task, and in my case it was even more so, because I had not only never designed low signal circuits before, but had I never operated a nanovoltmeter. That is quite an unfavorable starting position and jumping into the deep end rather than dipping my toes into the problematics. To ease my mind, I waited a few days to see how others reacted on the [eevblog forum](https://www.eevblog.com/forum/metrology/nanovolt-design-challenge-build-and-show-your-own-nv-meter-in-256-days/?all). I can't say that it encouraged me. On the other hand, I spent a few days researching online sources and studying the service manuals of proven test gear from reputable vendors. Too bad they stopped supplying us with schematics in early 90s of the last century; but even that material was very helpful in understanding both what the requirements are for such a meter, as well as the means to achieve it. ## NVM design, part 1 - design requirements Armed with new knowledge I started dissecting the challenge requirements. > Have local onboard power regulation. Single common DC (+9 to +24 VDC) or 110/220VAC mains input jack is expected. Okay, I think I can do this. On the other hand, any reasonable mains-powered voltmeter has to have an isolated PSU section which powers the input dividers/amplifiers and ADC, so that the measurement potential could be unrelated to the digital section with all the user and communication IO - which is needed to be earthed or somewhere close to that potential. This one calls for either DC or AC power, but it could be combined by having a PSU operating from an appropriate DC voltage (12V sounds like a good starting point) and attach a small AC/DC SMPS to provide power from mains. > Provide DC Voltage measurement ranges ±100 μV or below and include ±1V and ±10VDC range. This one looks innocent, but having both 10V and 100uV input on the same jacks implies either switching input amplifiers, or inserting a voltage divider into the signal path, preferably through a relay. Some older nanovoltmeters (Keithley model 181) had two different inputs - one for higher ranges, another one with low TEMF connector for sensitive ranges. > Have at least two user-accessible input channels for signal to be measured. Oh my, another relay. Relays are good, but may introduce offset errors into signals due to thermal voltages (TEMF, short for Thermal Electromotive Force) generated on the contacts, when the relay heats up from coil power. The voltages may be around a few microvolts down to nanovolts, definitely something to consider in this design. TEMF is the main enemy of the nanovoltmeter and this acronym will be used in following text a few more times. > Have low-thermal connection interface to minimize thermal EMF parasitic errors. TEMF again, I told you so. > Provide at least 512-digit resolution for each reading. Sounds reasonable. I've done long-scale ADC projects like [voltmeter](https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/) and [voltohmmeter](https://www.eevblog.com/forum/metrology/diy-6-digit-handheld-volohmmeter/msg2978912/#msg2978912) so perhaps I could recycle something and also bring something new to the table. I think commercial sigma-delta A-to-D converters would do the job too, but a DIY ADC definitely has more to it. > Ability to digitize input DC signal with resolution at least 10 nV and noise better than 30 nV peak to peak over at least 0.1-10 Hz bandwidth. More numeric requirements, nice. 30nVp-p in 10Hz bandwidth is not a very relaxed requirement - older meters like Keithley model 181 would not cut it, current models so-so. > Have autozero functionality to correct for static offsets. That is a logical requirement. I will put in some more effort by introducing autocalibration. > Have galvanic isolated analog front end, with isolation resistance to earth/chassis better than 10 GΩ. That is what I proposed earlier, too. > Device should have ADC (any type) integrated. This is likely to frame the project into standalone modus operandi. > Have good long-term stability and use ovenized DC voltage reference (LM399, LTZ1000 or LTFLU with oven). I wouldn't think of using anything worse than an LM399 (or ADR1399) anyway. > Provide RJ45 Ethernet and/or IEEE-488 GPIB interface for communications with external world / external equipment. Fair point. USB is simpler, though. > 40W total input power budget (friendly to battery operation for sensitive experiments) You wouldn't want your nanovoltmeter to consume more than 40W anyway. 40W is quite a bit of heat and it's not easy to dissipate it without introducing more TEMF errors. > Device should be fully operational as standalone device (e.g. no debuggers or external equipment attached to make it work). OK, fair. After a bit of optimization, I came up with this block diagram.  It's basically done to fit the requirements above, with a few spicy parts I added for extra fun. Input from either input connection is selected via an input multiplexor. There is also a third input, to be discussed later. This MUX passes the selected channel to a low noise amplifier (LNA) to be amplified and then routed via another MUX into the main amplifier. whose output is brought to the ADC. This ADC has a nominal 10V input range, so that the basic range with LNA is 10mV (10mV x 1000 = 10V). In order to have even more sensitive ranges, the main amplifier has option to switch to x1 (pass-through), x10 and x100 gain, combined into additional 1mV and 100uV ranges. When the LNA is bypassed, the input signal is brought directly to the main amplifier, allowing for 10V, 1V and 100mV ranges, seamlessly covering 100uV to 10V input range. That would make a nanovoltmeter already, but I added two more blocks - first is easy, a low-pass filter (also known as LPF) to cut down noise, especially on sensitive ranges. Another one is an auto-calibration block, which serves to decide the gain of both amplifiers. Ideally, the meter needs only to know its onboard 7V reference voltage and can derive lower ranges automatically without calibration/adjustment and keep it precise after resistors in dividers and amplifier drift due to age or temperature. The entire upper portion of the circuit is held behind an isolation barrier in order to keep the input terminals separated from the power supply potential - either external DC or mains voltage. The bottom section consists mainly of the PSU and digital circuitry, including user IO and communication channels, like Ethernet and USB. For the added fun factor I also included GPIB as a low priority subproject. ## NVM design, part 2 - divide and conquer Designing such an instrument, especially on a DIY base, is a lot of pingponging between mechanical and eletrical design. I could imagine how large the thing would be (say, an A4 page size as a footprint) and I knew I had to cram everything inside. Choosing a larger enclosure would give me much more freedom and other benefits (like easier dissipation of device heat, helping fight TEMF), but would be impractically large. Finding an appropriate enclosure wasn't easy - at first I thought of using G756 I used before in my [DIY SMU](https://github.com/jaromir-sukuba/J-SMU), but I preferred metal enclosures here - because of shielding from electrical interference, and with a steel enclosure even a bit of shielding from magnetic interference. Metal also helps with heat dissipation. Finally I settled on the 1EP802825 from Modushop. That was the right time to take a look at the electrical domain. The Earthy and floating parts (separated by an isolation barrier) have to be physically separated in sub-enclosures (that calls for two PCBs minimum) and in order to have easier debugging and modification of the circuit, I decided to separate the floating part into two PCBs. One would hold FPGA control, the reference and ADC, while another one would consist of both amplifiers and ACAL circuits. Since the enclosure is 80mm tall, there is no problem stacking at least two PCBs on top of each other, via pin headers and metric spacers. So, two PCBs for the floating part, one for the earthy part. The backside connectors have to be mounted somehow - here I added another PCB. The front panel pushbuttons also needed a PCB for mechanical reasons, that resulted in a total count of 5 PCBs. I named the PCBs with human names and gave them functionality: **Bart** - I felt like this one will be tricky and there will be problems. Contains LNA, main amplifier, ACAL dividers and MUXes. **Homer** - largest PCB, contains FPGA, ADC, references. Closely related to Bart. **Lisa** - communication board, back panel PCB **Meggie** - simplest PCB, just to hold buttons **Marge** - contains PSU to feed all other PCBs, plus digital circuits. With the electronics roughly separated into basic blocks, I returned to mechanical design. By the time I finished first sketches of the schematics files, I received the enclosure, so I could start with more practical details. It's much easier to visualize potential problems having the real enclosure in hand compared to studying 3D files (if any, right). For circuit separation I opted for two sheet metal sub-enclosures. . The smaller portion on right holding analog circuitry, the left portion holding earthy circuits - it's somehow shorter, to make room for a backpanel PCB. I designed a bunch of holes into the enclosures to allow mounting PCBs via metric spacers, and now having physical constraints, I jumped back to PCB design. ## NVM design, part 3 - selected details of circuit operation In this section I'll discuss a few selected design choices of this instrument. #### LNA (Bart board) I went through a few design iterations of the LNA and it took me roughly half of the development time. I tried DC-coupled JFET amplifiers, AC coupled JFET amplifiers in chopper configuration for DC operation as well as paralleling opamps. The parallel configuration brought me the least amount of headache and despite the insane amount of components used, it is not that expensive after all. As best in class, IF3602 JFETs are both expensive and suffer by huge parameter spread, making them quite an expensive solution. There are cheaper JFETs around, but their noise parameters mean more paralleled pieces - with problems they bring, for example binning and matching. More transistors or fewer low noise types also bring more gate capacitance, requiring more circuit support to diminish its influence. Enclosing the amplifier into chopper configuration brings more issues to solve - for example I had to deal with input current and temperature gradients increasing voltage offset. It's very likely that all those problems are solvable with more time and effort and would make an LNA with lower noise and drift than what I have in the current NVM, but at some point I decided to go a different way and built the LNA out of massively parallel off-the-shelf opamp amplifier. Integrated autozero/chopper opamps do have much better temperature stability and input current, so after a bit of searching and comparing I opted for MCP6V51 from Microchip, as the one with very good price/performance ratio. Typical input noise voltage is specified at 210nV in 10Hz bandwidth and I confirmed this experimentally by building a 35 piece opamp board first.  The noise parameters were in good agreement with the datasheet values, that gave me confidence to go this way. As calculated, I need at least 50 MCP6V51s to get under 30nV p-p criteria, so I opted for 100 pieces, in 10x10 matrix, as per the schematic below  Each of the first stage gain blocks (with 10 amplifiers in parallel noninverting configuration) is brought to a second stage summing amplifier, and all 10 of the second stage amplifiers are summed into a third, and final, amplifier, with an overall gain of 1000. The last stage summing amplifier is also used to inject a voltage to null the offset voltage of LNA. The Bart board has a DAC and its amplifiers (U119 and U120) for this reason. The DAC's second channel is designed to compensate for input current - by injecting a current of opposite sign into the LNA input. I measured the uncompensated current to be around 2nA and in my current hardware the injection resistor isn't fitted on the board. By using this feature, I expect a current well below 100pA. The LNA injects ground current into the ground net of the circuit, and the current is dependent on input voltage (and therefore output voltage, too). Ground current may cause unwanted voltage shifts between ground potentials of the circuit, especially at high gains. To counteract this ground current, amplifier with U121 is set up to source current of opposite polarity into the ground, into areas where the LNA resides. The Bart board is 4-layer, with internal layers being ground nets, for both electrical and thermal reasons. #### ADC (Homer board) The ADC is of the integrating, charge balancing type with residual integrator voltage reading. SN74LV4053 is used for integrator current steering, the integrator is of the classic two opamp composite type. The FPGA does multiple jobs here, apart from orchestrating actions around the ADC, it also provides an interface between isolated serial link and multiple digital outputs used to switch relays, multiplexer and analog filter and does startup timing for smooth PSU startup. I measured INL of ADC against a Solartron 7081 as reference. A 0-10V voltage sweep was provided by a DIY precision voltage source (LTZ1000A reference, AD5791B DAC). Measured INL graph:  The INL of this magnitude may not be obviously needed for this application, but I wanted to employ ACAL functionality, where voltage transfer between ranges expects good INL of the ADC, so I was after good linearity and spent some time honing it. #### PSU (Marge board) My first idea for the PSU was to use two back-to-back 50Hz transformers. One would provide a few volts (providing first isolation barrier and ground reference) and the second would step it up to the level appropriate for +-16V and 5V DC outputs. Later I expended this idea by using an audio frequency amplifier circuit to feed the second transformer and omitting the first transformer. Using an AF amplifier (fed by an appropriate oscillator) to drive the transformer has a few advantages - the whole circuit could be powered from a single DC voltage and the oscillation frequency can be adjusted to find a good compromise between leakage and efficiency. Using classic linear amplifiers would bring way too much thermal dissipation into the enclosure, so I opted for the cheap and plentiful TPS3116 D-class amplifier. The oscillator signal - either from a local single opamp multivibrator or amplified signal provided by the MCU - is shaped by a series of lowpass filters, so that the amplifier is fed by a low harmonic content signal. Transformer secondary is brought to a fairly standard set of regulators - LM317/337 and 7805. I measured ground leakage from the isolated PSU section and its efficiency as function of driving frequency.  As per expectations, a lower frequency also brings lower leakage current, but going too low causes efficiency to plummet at some point. I opted for 48Hz, where I measured leakage well below 200nA p-p. At this level, leakage measurement is very sensitive to nearby electric fields and conducted interference. After enclosing the test setup in a shielded box, the measured leakage fell to 40nA p-p, indicating the previous measurement was too pessimistic. I believe even the 40nA figure is pessimistic still and influenced by the shielding setup and the oscilloscope I used. For proper test results I'd need a larger shielded cage and a battery powered oscilloscope, but I didn't want to go that far. The PSU design brought interesting detail to the game. In case of overload, TPS3116 will turn off the load drive. That sounds innocent, but may be problemtic in this case - because after powerup the reference is cold, so the heater takes a significant amount of current during powerup. To add insult to injury, all decoupling/bulk capacitors are discharged, even more increasing the powerup current spike. The spike causes TPS3116 to shut down for a moment, then it tries to restart the load, ending up in the same large spike, repeating again and again. To mitigate this issue, two fixes were made: - PSU driving starts from higher frequency, slowly (over course of a few seconds) it descends to the final 48Hz value. Voltage on the isolated secondary ramps up much slower, allowing circuits to power up smoothly. - Voltage reference heating current (large current spike when left untreated) and LNA power supply voltage is held off until 10 seconds after FPGA power gets stable, at which point heater current is enbled, and LNA power turns on two seconds later. ## Mechanical parts While the enclosure is centered around the Modushop enclosure, a few more mechanical parts were needed. #### Reference cover This two-part 3D printed component prevents airflows around ADR1399 reference, decreasing its noise somehow.   #### Lisa board holder This 3D printed component keeps Lisa board in its place on back panel.   #### LNA cover This 3D printed component provides insulation of LNA board area from airflows.   The amount of influence on the readings was suprising to me. Here are two graphs of the shorted input measurement, one with cover, one without, the RMS noise voltage is nearly twofold for naked LNA.  #### Side P ... ...

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