MipsCPU-SystemVerilog
所属分类：VHDL/FPGA/Verilog
开发工具：SystemVerilog
文件大小：1192KB
下载次数：0
上传日期：2022-11-03 08:33:25
上 传 者：
sh-1993
说明： MIPS处理器，带高速缓存、多循环存储器和浮点协处理器
(MIPS processor with cache and multicycle memory and floating-point coprocessor)
文件列表:
323src (0, 2022-11-03)
323src\dff.sv (319, 2022-11-03)
323src\memory.sv (1816, 2022-11-03)
323src\mips_machine.sv (2912, 2022-11-03)
323src\regfile.sv (1791, 2022-11-03)
323src\sim_main.cpp (973, 2022-11-03)
License (1071, 2022-11-03)
Makefile (1503, 2022-11-03)
documents (0, 2022-11-03)
documents\Project's Document.pdf (387170, 2022-11-03)
documents\Project-Phase-1.pdf (150751, 2022-11-03)
documents\Project-Phase-2.pdf (104518, 2022-11-03)
documents\Project-Phase-3.pdf (181024, 2022-11-03)
documents\Project-Phase-4.pdf (589902, 2022-11-03)
output (0, 2022-11-03)
src (0, 2022-11-03)
src\ALU.sv (3813, 2022-11-03)
src\ALU_floating_point.sv (17409, 2022-11-03)
src\EX.sv (2990, 2022-11-03)
src\ID.sv (4056, 2022-11-03)
src\IF.sv (1076, 2022-11-03)
src\MEM.sv (3347, 2022-11-03)
src\WB.sv (3156, 2022-11-03)
src\arithmetic_shifter.sv (630, 2022-11-03)
src\buffer_EX-MEM.sv (7907, 2022-11-03)
src\buffer_ID-EX.sv (9311, 2022-11-03)
src\buffer_IF-ID.sv (1029, 2022-11-03)
src\buffer_MEM-WB.sv (5884, 2022-11-03)
src\cache.sv (3162, 2022-11-03)
src\cache_controller.sv (5655, 2022-11-03)
src\controller.sv (20565, 2022-11-03)
src\lock_dff.sv (352, 2022-11-03)
src\mips_core.sv (18488, 2022-11-03)
src\pc_controller.sv (1322, 2022-11-03)
src\sign_extender.sv (376, 2022-11-03)
src\signed_comparator.sv (566, 2022-11-03)
... ...
# MIPS Processor
## About
In this project, we design a simple MIPS processor in phase one with `SystemVerilog,` After that, we add multicycle memory and cache in phase two, and then in phase three, we add pipelines to the MIPS machine. In phase four, we design a floating-point coprocessor and register file for storing floating-point numbers.
In the end, we have written a series of tests to check the correct operation of the processor in the test folder, which you can see in the `test` folder.
## Documentation
You can see all doucuments about design and codes in `documemts`.
## Requirement
To run the project, you must have Docker installed on your system.
## Commands
You can use the project by running these commands in the root of the project.
`make assemble`: assemble all verilog files.
`make compile`: compile modules.
`make verify [test name]`: run specific test.
`make verify-all`: run all tests.
`make clean`: delete all compiled moudels.
## Maintainers
- [Iman Mohammadi](https://github.com/Imanm02)
- [Mehdi Alizadeh](https://github.com/alizademhdi)
- [Mohammad Moshtaghi](https://github.com/MohammadMoshtagh)
- [Behzad Nabawi](https://github.com/behzadnabawi)
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