buffered-cpu-interfact.tar
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：8KB
下载次数：10
上传日期：2011-10-14 11:18:05
上 传 者：
awublack
说明： This is a fully synchronous (single clock domain, no asynchronous resets) UART with a FIFO buffered cpu interfact
文件列表:
uart_fifo_cpu_if_sv_testbench (0, 2011-10-14)
uart_fifo_cpu_if_sv_testbench\tags (0, 2011-10-14)
uart_fifo_cpu_if_sv_testbench\branches (0, 2011-10-14)
uart_fifo_cpu_if_sv_testbench\trunk (0, 2011-10-14)
uart_fifo_cpu_if_sv_testbench\trunk\sim (0, 2011-10-14)
uart_fifo_cpu_if_sv_testbench\trunk\bench (0, 2011-10-14)
uart_fifo_cpu_if_sv_testbench\trunk\bench\uart_tb.sv (13034, 2011-01-04)
uart_fifo_cpu_if_sv_testbench\trunk\rtl (0, 2011-10-14)
uart_fifo_cpu_if_sv_testbench\trunk\rtl\uart.vhd (19497, 2011-01-04)
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