my_ram_change
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：5330KB
下载次数：14
上传日期：2011-10-19 19:47:49
上 传 者：
liubenlu
说明： 该文档实现了向BRAM中写入数据。1024个为一组，前1000个存1，后24个存0.共存入100组。
(This document implements write data to the BRAM. 1024 as a group, the first 1000 deposit 1, deposit after 24 0 100 group were deposited.)
文件列表:
my_ram_change\blk_mem_gen_ds512.pdf (1257529, 2010-10-10)
my_ram_change\coregen.cgp (528, 2010-10-10)
my_ram_change\coregen.log (0, 2010-10-10)
my_ram_change\coregen.rsp (281, 2010-10-10)
my_ram_change\device_usage_statistics.html (76964, 2010-10-08)
my_ram_change\fff.cdc (599, 2010-09-22)
my_ram_change\ffff.v (529, 2010-09-25)
my_ram_change\initial.v (980, 2010-09-22)
my_ram_change\my_ram.gise (20530, 2010-10-18)
my_ram_change\my_ram.ise (98194, 2010-10-18)
my_ram_change\my_ram.ntrc_log (1653, 2010-10-09)
my_ram_change\my_ram.restore (53668, 2010-09-25)
my_ram_change\my_ram.xise (51103, 2010-10-09)
my_ram_change\my_ram_ise11migration.zip (2645545, 2010-09-25)
my_ram_change\my_ram_pa_ports.v (451, 2010-10-09)
my_ram_change\my_ram_xdb\cst.xbcd (1271, 2010-10-09)
my_ram_change\my_ram_xdb\tmp\ise\version (138, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject (223, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject_StrTbl (24, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\__stored_object_table__ (60, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl (27, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl_StrTbl (3817, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigator\dpm_project_main\dpm_project_main (25, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigator\dpm_project_main\dpm_project_main_StrTbl (10, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CSourceProcessView (59, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CSourceProcessView_StrTbl (10, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CViewSelector (27, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CViewSelector_StrTbl (26, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\File-SynthesisOnly (72, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\File-SynthesisOnly_StrTbl (38, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\GuiProjectData (230, 2010-09-25)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\GuiProjectData_StrTbl (361, 2010-09-25)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Library-SynthesisOnly (66, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Library-SynthesisOnly_StrTbl (24, 2010-10-18)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Process-BehavioralSim- (76, 2010-10-09)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Process-BehavioralSim-DESUT_VERILOG (78, 2010-10-09)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Process-BehavioralSim-DESUT_VERILOG_StrTbl (343, 2010-10-09)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Process-BehavioralSim-DESUT_XCO (74, 2010-10-09)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Process-BehavioralSim-DESUT_XCO_StrTbl (141, 2010-10-09)
my_ram_change\my_ram_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\Process-BehavioralSim-_StrTbl (328, 2010-10-09)
... ...
The following files were generated for 'ram_32' in directory
C:\Documents and Settings\Administrator\my_ram\
ram_32_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
blk_mem_gen_ds512.pdf:
Please see the core data sheet.
ram_32.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
ram_32.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
ram_32.ise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
ram_32.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
ram_32.sym:
Please see the core data sheet.
ram_32.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
ram_32.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
ram_32.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
ram_32.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
ram_32.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
ram_32.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
ram_32_readme.txt:
Text file indicating the files generated and how they are used.
ram_32_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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