ram_fifo_ram
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：7994KB
下载次数：62
上传日期：2011-10-22 09:11:14
上 传 者：
岚风秋叶
说明： 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试
(Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim)
文件列表:
ram_fifo_ram (0, 2011-10-20)
ram_fifo_ram\cis.gise (9133, 2011-10-20)
ram_fifo_ram\cis.xise (33736, 2011-10-20)
ram_fifo_ram\coregen.cgc (2049, 2011-10-20)
ram_fifo_ram\coregen.cgp (518, 2011-10-20)
ram_fifo_ram\dcm.tfi (242, 2011-10-20)
ram_fifo_ram\dcm.v (3088, 2011-10-20)
ram_fifo_ram\dcm_arwz.ucf (728, 2011-10-20)
ram_fifo_ram\devide.v (1036, 2011-10-20)
ram_fifo_ram\ipcore_dir (0, 2011-10-20)
ram_fifo_ram\ipcore_dir\blk_mem_gen_ds512.pdf (3259182, 2011-10-20)
ram_fifo_ram\ipcore_dir\dcm.cgc (6776, 2011-10-20)
ram_fifo_ram\ipcore_dir\dcm.cgp (525, 2011-10-20)
ram_fifo_ram\ipcore_dir\dcm.v (3104, 2011-10-20)
ram_fifo_ram\ipcore_dir\dcm.xaw (3102, 2011-10-20)
ram_fifo_ram\ipcore_dir\dcm_arwz.ucf (728, 2011-10-20)
ram_fifo_ram\ipcore_dir\dcm_flist.txt (79, 2011-10-20)
ram_fifo_ram\ipcore_dir\dcm_xmdf.tcl (1652, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.asy (968, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.cgc (18408, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.cgp (525, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.gise (1345, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.ngc (87661, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.v (5447, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.veo (3113, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.vhd (5745, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.vho (3580, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.xco (2579, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo.xise (5019, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo_flist.txt (223, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo_generator_ug175.pdf (2895895, 2011-10-20)
ram_fifo_ram\ipcore_dir\fifo_xmdf.tcl (2969, 2011-10-20)
ram_fifo_ram\ipcore_dir\ram.asy (774, 2011-10-20)
ram_fifo_ram\ipcore_dir\ram.cgc (19014, 2011-10-20)
ram_fifo_ram\ipcore_dir\ram.cgp (525, 2011-10-20)
ram_fifo_ram\ipcore_dir\ram.gise (1341, 2011-10-20)
ram_fifo_ram\ipcore_dir\ram.ngc (17676, 2011-10-20)
ram_fifo_ram\ipcore_dir\ram.v (4870, 2011-10-20)
... ...
The following files were generated for 'dcm' in directory
E:\led\cis\ipcore_dir\
dcm_readme.txt:
Text file indicating the files generated and how they are used.
dcm_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
dcm_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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